IDT to Detail Innovative Phase-Locked Loop Architecture at 2005 International Solid-State Circuits Conference
SAN FRANCISCO, International Solid State Circuits Conference, February 9, 2005 — IDT™ (Integrated Device Technology, Inc.; NASDAQ: IDTI) today announced that it will unveil details of a new innovative phase-locked loop (PLL) architecture at the 2005 International Solid State Circuits Conference (ISSCC). The new architecture is the first to use a current mode filter in a PLL, enabling a very easy-to-design structure that also keeps the bandwidth and jitter performance independent of process, voltage, temperature (PVT) and multiplication factor. The result is a more flexible and reliable clock generation solution. IDT intends to apply this patent-pending technology to future clock products. IDT also announced that this paper represents the first ever to be accepted from China for presentation at ISSCC. The IDT paper, “A Self-Biased PLL with Current Mode Filter for Clock Generation,” will be presented February 9, 2005 at 11:15 a.m. in Salon 9 at the San Francisco Marriott Hotel.
“Annually, ISSCC provides semiconductor technologists a prestigious forum for the presentation of advances in solid-state circuits and systems, and we are honored to have been invited to share the details of our innovative self-biased PLL architecture at this conference,” said Dr. Zhongyuan Chang, general manager for IDT-Newave Technology. “This new design builds on the IDT technology leadership in the PC clock arena, where we were the first to introduce a four PLL-based PC clock device. IDT is also proud to represent a significant milestone for the design community in China and we look forward to the acceptance of many more papers from China at future ISSCC events.”
The IDT-Newave design center is located in Shanghai, China. IDT acquired Newave, a Chinese semiconductor firm, in 2001 to accelerate its investment in the growing Asian semiconductor industry and the telecommunications market. Over the past few years, the design center has expanded its focus beyond the telecom market to develop technologies across multiple product areas.
Phil Bourekas, IDT vice president of worldwide marketing, said, “We continue to be impressed with the talent demonstrated by our IDT Shanghai design team. In addition to the new self-biased PLL technology, the team has developed innovative PC clock and other advanced clocking products. The team is also responsible for some of our flow-control management products, including the award-winning SPI-exchange devices, and supports our corporate initiative to apply advanced, high-speed serial I/O across multiple product families.”
There has been growing interest in clock generators with arbitrary clock output for such applications as PC and digital consumer systems. A widely adopted approach has been to use a multiplying PLL to generate different output frequencies with a single reference clock by setting only the multiplication factor. One problem with this approach is that both the PLL bandwidth and jitter performance vary with the multiplication factor in classic PLL designs. For many applications, it is desirable to keep the bandwidth and jitter performance independent of PVT and multiplication factor. Additionally, with a conventional PLL, a PC clock can only provide limited over-clocking capabilities. If spread spectrum clocking (SSC) is turned on, the SSC depth (magnitude) is affected while over-clocking. Moreover, the PLL musthave small die size and low power consumption to reduce device cost.
To overcome these challenges, IDT has developed a self-biased PLL utilizing a current mode filter to make the PLL bandwidth independent of PVT and multiplication factor. Unlike existing solutions, the IDT PLL does not need a current steering digital-to-analog converter (DAC) or a sampled feed-forward network, resulting in a simple and robust design with low power and a die size as much as 15 percent smaller than current solutions. Likewise, the new multiplication-independent architecture provides a robust structure for over-clocking. With this design, only the ring oscillator limits the over-clocking capabilities and SSC is not affected.