IDT RapidIO® 40-100 Gbps Interconnect Portfolio
IDT is the industry’s leading supplier of RapidIO® interconnect solutions, providing a broad portfolio of switches, bridges/NICs, IP, and development platforms for wireless, data center, high performance computing, aerospace & defense, video, imaging, and industrial markets. IDT’s RapidIO 100 G technology platform will move performance initially to 40 Gbps per port and and scales to 100Gbps, enabling chip to chip, board to board and system to system scale out with ultra low latency and energy efficiency.
Products from this technology platform are based initially on the RapidIO 10xN specification released by RapidIO.org and will conform to future editions scaling to 25 Gbaud per serial lane supporting ports up to 100 Gbps. The product portfolio will also support the Open Compute Project High Performance Computing fabric interconnect scaling up to 100 Gbps.
Today, RapidIO interconnect is used in 100% of 4G base station deployments and in a variety of aerospace, military, embedded, imaging and industrial production solutions.
The RapidIO Interconnect connects multi processor systems in a low latency, scalable, energy efficient way. It is natively integrated on a variety of Systems on Chip (SoCs), NPUs, FPGAs, CPUs and DSPs and allows them to be networked with a high-performance, packet-switched, fabric approach.
In the past decade, a number of experts from the embedded systems world created RapidIO to optimize the manner in which microprocessors, FPGAs, digital signal processors, ASICs, entire boards and entire chassis were connected. The intention was to design an interconnect that allowed these elements to speak to one another using any networking topology, with low latency, low power and an architecture than would simplify the design of application level software. For the reasons mentioned, above, it was clear, that applications would very rarely be built in embedded systems with single processors only. Moore’s law simply could not catch up with application needs. This led to the inception of RapidIO. As Computing needs scale at the application level, interconnect throughput, latency scalability and power become the biggest bottleneck to do application processing in real time/near real time. For example one of the biggest impediments to get to Exascale super computing is the bottleneck created by the interconnect. This is what RapidIO was created to optimize.
Because RapidIO was built from the ground up for multi-processor peer-to-peer networks, it inherently comes with the following attributes.
- Optimized for unified fabric interfaces to support any topology: direct connect, star, dual star, mesh, 2D and 3D Taurus etc.
- 95% protocol efficiency between payload and header meaning power and SerDes is used to actually transport data, lowering system level costs.
- Reliable transmission built into the protocol at the hardware level
- Sub micro-second end-to-end packet delivery from memory to memory
- 100 ns cut through switching latency
- No processor overhead to terminate the protocol with silicon terminated protocol stack
- High performance messaging for transmitting large amounts of data
- Push architecture with the option for every processor in the system to have its own memory subsystem
- Up to 40 Gbps per port scaling to 100 Gbps in roadmap parts
RapidIO 10xN builds on previous generations of RapidIO and supports serial link speeds of up to 10.3125 Gbaud, resulting in the development of switches and bridges with single port bandwidths of 40 Gbps. The specification is scalable, setting the path for single lane speeds of up to 25 Gbaud and port bandwidth in x4 mode of up to 100 Gbps and is also backward compatible to Gen1 and Gen2 ecosystems of semiconductors, boards and systems.
Comparison with Other Interconnect Protocols
- Highest performance embedded serial interconnect for native fabric interfaces with up to 10.3125 Gbaud per lane moving to 25 Gbaud
- Highest protocol efficiency in embedded systems with 94% payload versus header efficiency
- Serial RapidIO standard supports arbitrary system topology with true peer-to-peer hardware terminated networking
- No TCP termination processor overhead as is the case for Ethernet
- RapidIO messaging support for transfers of large blocks of data
- RapidIO has native termination of the protocol in a large ecosystem of processors, DSPs, FPGAs, ASIC, requiring no NICs as is required for Ethernet and Inifiniband, resulting in very large scale dense computing solutions
- Design high performance backplanes with 40 Gbps data rate per port, 10.3125 Gbaud per lane
- Scale beyond 40 Gbps per port up to 100 Gbps
- No TCP offload needed reducing overall latency and system level power
- 40 Gbps can be terminated in less than 0.7 square millimeters in 28 nm technology making it attractive to include native RapidIO termination on endpoints
- Lowest power per payload bit vs. other interconnect protocols, <250mW per 10Gbps
- RapidIO standard supports arbitrary system topology with true peer-to-peer networking with no limitation like in PCIe
- RapidIO Messaging Support for transfers
- Wireless: Baseband cards and backplanes in 5G, LTE Advanced, LTE , WCDMA High Performance Computing and Supercomputing
- Data Center Analytics and Server
- Mobile Edge Computing
- Defense and aerospace: Radar, sonar and navigations systems
- Medical imaging: CT scanners, MRIs
- Industrial Automation
- Video: Teleconferencing
IDT Products with 10xN Technology on Roadmap
- Wireless/Embedded Switches, Data Center Switches, PCIe to RapidIO NIC/Bridge Devices, RapidIO 10-25xN Endpoint IP
- Embedded Switch IP
RapidIO 10xN IP
As part of its RapidIO 40-100 Gbps portfolio, IDT is offering endpoint intellectual property (IP) which allows DSPs, ASICs, CPU, GPU and FPGA to easily access RapidIO networks. By using IDT RapidIO 10xN IP, customers are assured of interoperability with the number one supplier of RapidIO switches: IDT.
IDT RapidIO 10xN IP endpoint IP works seamlessly with all silicon in the ecosystem that has been tested pre-silicon with the RapidIO Trade Association’s bus functional model and post-silicon and will also follow the trajectory of technology progression in the Open Compute Project High Performance Computing initiative
The solution allows for termination of 40 Gbps in hardware with no processor cycles needed with ultra low latency with no need for TCP offload, allowing for massively scalable multi processor systems.
IDT RapidIO 10xN IP Features:
- RapidIO Gen1 Gen2 and 10xN (Gen3) compliant (v1.3, v2.1, and 3.0)
- Used in IDT’s 10xN switching and bridging (NIC) roadmap offering
- Pre silicon interoperability with IDT switching silicon
- Pre-silicon tested versus RapidIO Trade Association Bus Functional Model
- Can be used in DSPs, GPU,, CPUs and ASICs, FPGAs (hard core) synthesizable from RTL
- Target 40 nm or lower CMOS process technology
- Supports x1, x2, x4 ports, maximum of 40 Gbps
- Implements PHY Layer
- Supports PCS layers and generic PMA layer
- Includes SERDES I/F
- Implements Transport Layer
- CRC checking, destID Processing
- VOQ selection, Packet filtering
- Supports in-/egress Packet Buffering
- Temporary storage on ingress and egress
- Supports packet retry/ack
- Supports cut-through packet transfer
- Incorporates end-point Fabric Scheduler
- Support Maintenance packet processing
- Flexible Modes of Operation
- Register configuration through AMBA-AHB 2.0 like i/f
- Compile Time parameters
- Comprehensive clocking and error management
- Long reach support 100 cm over 2 connectors over PCB with clean eye diagram
- Logical Layer functionality can be provided based on customization
- Embedded Switching functionality can be provided based on customization
- Available now, approx 0.7 square mm in 28 nm technology
News Release, July 8, 2014: “IDT and eSilicon to Collaborate on Next-Generation RapidIO Switches”
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