CrystalFree™ Solid State Oscillator Technology White Paper
Introduction
A high-accuracy, low-noise and low-power CrystalFree™ Solid-State oscillator enables frequency control devices to be migrated to the lowest possible cost structure using the ubiquitous CMOS technology. However, CMOS technology does not include high-Q (Quality factor) components. For example the Q-factor of an integrated inductor is in the range of 10-20. However, CMOS technology supports the design of high-frequency oscillators. Thus, the Qfrequency (Q-f) product in CMOS Oscillators is high. Consequently, CMOS oscillators can achieve low-noise, despite the low-Q of the resonator compared to MEMS Oscillators and Crystal Oscillators. Due to the Qfrequency (Q-f) product being same among the different technologies, the performance among the different technologies is similar. CMOS oscillators even with low Q due to the CMOS process can achieve similar performance as the crystal oscillators and the MEMS oscillators at an advantage of the lowest cost due to the all silicon process. The remaining challenge with CMOS oscillators involves minimizing frequency drift and achieving high frequency stability which will be discussed in this paper.
Frequency Drift in a CMOS Oscillator
The natural resonant frequency of a CMOS LC Oscillator (LCO) is
where ' L' is the net tank inductance and ' C ' is the net tank capacitance.
Due to resistive losses in both the inductor and capacitor, the actual resonant frequency is given by:
where RL and RC are the losses in the coil and the capacitor respectively. Both exhibit temperature coefficients.
Typically, RL is significantly larger than RC. Consequently, the equation can be simplified to:
RL (T) causes temperature induced frequency drift which is negative and concave down.
Design Approaches
If a resistive loss, RC, is deliberately introduced to the tank capacitance, C, the frequency drift due to the resistive loss in the coil, RL, can be cancelled. This observation led to the development of the passive compensation approach of adding lossy capacitance to compensate for the temperature frequency drift due to the coil. This approach has enabled CMOS Oscillators to achieve total frequency stability under ±100 ppm over -20°C to70°C, all operating conditions and lifetime while dissipating less than 4mW. Fig. 1 presents the frequency stability of 40 devices which were selected randomly from the production test flow. No device exceeds ± 75 ppm frequency error over temperature.
Fig 1: LC Oscillator Frequency Stability of 40 random devices over temperature
LC Oscillator Architecture
The resonant frequency of the LC oscillator is 3GHz to increase the quality-factor of the inductor. A lossy capacitance is introduced into the tank, such that it matches the loss in the coil and hence the temperature coefficient (TCf) due to the coil in the LC oscillator can be cancelled. This approach enables the temperature coefficient to be compensated passively, thus minimizing power dissipation while reducing noise from what would otherwise be the active compensation circuitry. An array of programmable thin-film capacitors (Cf[X:0]) serves to trim the offset due to process variation through the corresponding switches, TR[X:0] as shown in Fig. 2. The remaining programmable frequency array of thin-film capacitors (Cf[Y:0]) includes resistors (RC[Y:0]) in series with each capacitor such that a loss can be deliberately introduced into the capacitive network through switches TC[Y:0]. A programmable divider array divides the LC oscillator resonant frequency to enable the device to support frequencies from 1–200 MHz. The system architecture includes a programmable integer divider array and nonvolatile memory (NVM) for storing trimming, compensation and configuration coefficients.
Package Induced Frequency Drift
The unpackaged LC oscillator silicon die shown in Fig. 3 is subject to several influences that give rise to frequency drift resulting in lower frequency stability.
For example, incident electromagnetic radiation can pull the self-resonant frequency. Light can introduce an undesired offset in the bias circuitry due to photo current. Additionally, fringing magnetic (B) fields from the coil and electric (E) fields from the net tank capacitance exist as illustrated in Fig. 4
The fringing electromagnetic fields emanating from the die can be perturbed by the surrounding package or environment and induce frequency drift. Referring to Fig. 4, the B-field that radiates from the coil can extend beyond the boundary of the package. Consequently, if the field is modulated by a permeable material or terminated with a metal, the frequency will drift. Similarly, a parasitic capacitance is created by the stray E-field from the device. Any changes in the permittivity of the molding compound of the package can induce frequency drift. Left uncontained, each mechanism can induce frequency drift exceeding hundreds of ppm.
Faraday Shield and Frequency Stability
To overcome the frequency drift due to the package and surrounding environment, a low-cost, wafer-scale post-process has been developed (Faraday Shield) to serve as a stress buffer between the top of the die and the package. The Faraday shield contains and terminates the fringing electromagnetic fields, thus enabling the silicon die to be tested at wafer and packaged with nearly any assembly technique in a plastic package, multi-chip package (MCP) or chip on board (CoB). Faraday shield includes a thick dielectric mesa as shown in Fig. 5. The top of the dielectric mesa is electroplated with several microns of Cu, which is sufficiently thick to contain the fringing magnetic B-field at 3GHz. Similarly, the backside is metalized with several microns of Aluminum to contain the fringing electromagnetic fields. The Faraday shield terminates the fringing magnetic B-field on both sides of the die as shown in the figure. Additionally, the hermetically-sealed dielectric material presents a constant permittivity to the fringing electric- field hence controlling the parasitic capacitance.
This latest generation of the Faraday shield, pictured in Fig. 6, enables LC Oscillators to achieve ± 100 ppm frequency stability over -20°C to70°C .
High-Volume Production Testing
Each CMOS oscillator must be trimmed for frequency offset and temperature-compensated. To reduce cost, a 126-site massively-parallel probe [Fig. 7] has been developed which performs a two-temperature insertion to ensure the best temperature compensation is set on each device to achieve total frequency stability under ± 100 ppm over -20°C to70°C, all operating conditions and lifetime. Production test throughput is 30 kU / hr including both temperature insertions.
Performance Results
Measured results of the single-sideband (SSB) phase noise power spectral density (PSD) for a device configured to 125 MHz is shown in Fig. 8. The noise floor is below -145dBc/Hz. The integrated RMS phase jitter from 12 kHz to 20 MHz is 2 ps, using a brick-wall filter. No significant spurs were observed in the spectrum. Overall, the phase noise performance is excellent with extremely low power dissipation consuming only 2mA, primarily due to the passive temperature compensation technique as discussed in the earlier section on Design Approaches.
Conclusion
CrystalFree Solid-State oscillators built on standard CMOS technology is able to achieve total frequency stability under ± 100 ppm over -20°C to70°C, all operating conditions and lifetime with excellent phase noise performance consuming only 2 mA of current. With passive temperature compensation technique using lossy capacitance to cancel the frequency drift due to the coil, these oscillators are able to provide a stable frequency source. The Faraday shield contains and terminates the fringing electromagnetic fields to prevent frequency drift due to the surrounding environment. With this all silicon technology, CrystalFree Solid-State oscillators have also recently proven to achieve ± 50 ppm accuracy over 0°C to 70°C with the lowest cost in the industry.
This white paper was written by the IDT Silicon Frequency Control Group - by Michael McCorquodale and Baljit Chandhoke.
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