Port Synchronizer for IEEE 1588 and 10G/40G Synchronous Ethernet

The 82P33741 Port Synchronizer for IEEE 1588 and 10G/40G Synchronous Ethernet provides tools to manage timing references, clock conversion and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE). The device supports up to three independent timing paths for: IEEE 1588 clock generation; SyncE clock generation; and general purpose frequency translation. The device outputs low-jitter clocks that can directly synchronize 40GBASE-R, 10GBASE-R and 10GBASE-W and lower-rate Ethernet interfaces; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).

► Download the Altera and IDT Synchronous Ethernet Solution for ITU-T G.8262 white paper

Features

  • Supports 3 independent timing paths: IEEE 1588, physical layer (SyncE, SONET/SDH, PDH, CPRI/OBSAI) and recovered line clock
  • Phase synchronizes IEEE 1588 TSUs (Time Stamp Units) at network ports with redundant system-wide IEEE 1588 clock and sync pulse pairs: 1PPS (Pulse Per Second) sync pulses
  • Precise 1PPS edge alignment is supported with programmable input-to-input, input-to-output and output-to-output phase delays: sub-ns resolution
  • Frequency synchronizes physical layer ports with redundant system-wide frequency references
  • Generates clocks for: 10GBASE-R, 10GBASE-W, 40GBASE-R and CPRI/OBSAI interfaces without external jitter attenuators: jitter generation <0.3 ps RMS (10 kHz to 20 MHz)
  • Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
  • Prevents time errors and PHY bit errors with automatic reference switching, optional hitless reference switching and revertive or non-revertive reference switching
  • DPLLs lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI/OBSAI and GNSS frequencies using fractional-N input dividers
  • Automatically loads configuration from an external EPROM after reset without processor intervention
  • 144 pin CABGA package

Product Options

Orderable Part ID Part Status Pkg. Code Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
82P33741BAG Active BAG144 C Yes Tray Availability
82P33741BAG8 Active BAG144 C Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
82P33741 Datasheet - Datasheet PDF 783 KB Dec 8, 2016
Application Notes & White Papers
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment - Application Note PDF 175 KB Nov 20, 2016
AN-861 Recommended Crystals for IDT VCXO-based Synchronization PLLs - Application Note PDF 214 KB Oct 27, 2016
AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL - Application Note PDF 77 KB Oct 27, 2016
AN-835 Differential Input with VCMR being VIH Referenced - Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units - Application Note PDF 476 KB Apr 23, 2014
AN-946 Using a 19.2MHz System Clock with 82P337xx/8xx/9xx - Application Note PDF 165 KB Aug 22, 2016
AN-828 Termination - LVPECL - Application Note PDF 229 KB Jul 5, 2016
ITU-T Profiles for IEEE 1588 - White Paper PDF 1.17 MB Oct 22, 2015
AN-846 Termination - LVDS - Application Note PDF 50 KB May 12, 2014
AN-845 Termination - LVCMOS - Application Note PDF 62 KB May 12, 2014
AN-844 Termination - AC Coupling Clock Receivers - Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection - Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals - Application Note PDF 349 KB May 7, 2014
AN-839 RMS Phase Jitter - Application Note PDF 149 KB May 6, 2014
AN-838 Peak-to-Peak Jitter Calculations - Application Note PDF 32 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels - Application Note PDF 37 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter - Application Note PDF 1.06 MB Apr 23, 2014
AN-806 Power Supply Noise Rejection - Application Note PDF 353 KB Jan 14, 2014
AN-805 Recommended Ferrite Beads - Application Note PDF 38 KB Jan 14, 2014
AN-801 Crystal-High Drive Level - Application Note PDF 109 KB Jan 14, 2014
Other
Timing Fabric for Next Generation Communications Equipment Overview 日本語, 简体中文 Overview PDF 1.31 MB Feb 21, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016
Timing Fabric for Communications Equipment Overview - Overview PDF 263 KB Dec 10, 2015

Software & Tools

Title Other Languages Type Format File Size Date
82P33741 BSDL - Model - BSDL BSD 20 KB Jan 15, 2015
82P33741 IBIS - Model - IBIS IBS 1.04 MB Dec 14, 2014

Evaluation Boards

Part Number Title Sort ascending
82EBP33831 Evaluation Board for 82P33831 Synchronization Management Unit for IEEE 1588 and 10G/40G Synchronous Ethernet