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82V3002A - Block Diagram
82V3002A - Pinout


WAN PLL With Dual Reference Inputs

The 82V3002A is a WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS clocks and framing signals that are phase locked to a 2.048 MHz, 1.544 MHz or 8 kHz input reference. The 82V3002A provides eight types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C32o) and six types of framing signals (F0o, F8o, F16o, F32o, RSP, TSP) for the multitrunk T1 and E1 primary rate transmission links. The 82V3002A is compliant with AT&T TR62411, Telcordia GR- 1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4, ETSI ETS 300 011, ITU-T G.813 Option 1 for 2048 kbit/s interface, and ITU-T G.812 Type IV clocks for 1544 kbit/s interface and 2048 kbit/s interface. It meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency accuracy and MTIE (Maximum Time Interval Error) requirements for these specifications. The 82V3002A can be used in synchronization and timing control for T1 and E1 systems, or used as ST-BUS clock and frame pulse sources. It can also be used in access switch, access routers, ATM edge switches, wireless base station controllers, or IADs (Integrated Access Devices), PBXs and line cards.


  • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces
  • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces
  • Supports ITU-T G.812 Type IV clocks for 1544 kbit/s interface and 2048 kbit/s interfaces
  • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface
  • Selectable input reference signal: 8 kHz, 1.544 MHz or 2.048 MHz
  • Accepts reference inputs from two independent sources
  • Provides eight types of clock signals: C1.5o, C3o, C2o, C4o, C6o, C8o, C16o and C32o
  • Provides six types of 8 kHz framing pulses: F0o, F8o, F16o, F32o, RSP and TSP
  • Holdover frequency accuracy of 0.025 ppm
  • Phase slope of 5 ns/125 ?s
  • Attenuates wander from 2.1 Hz
  • Fast Lock mode
  • Provides Time Interval Error (TIE) correction
  • MTIE of 600 ns
  • JTAG boundary scan
  • Holdover status indication
  • Freerun status indication
  • Normal status indication
  • Lock status indication
  • Input primary reference quality indication
  • 3.3 V operation with 5 V tolerant I/O
  • Package available: 56-pin SSOP (Green option available)

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)App Jitter ComplianceProg. Clock
12, 14LVCMOS0.008000 - 32.768000, 0.008000, 1.544000, 2.048000, 3.088000, 4.096000, 6.312000, 8.192000, 16.384000, 32.7680000.002000 - 32.768000, 0.008000, 1.544000, 2.0480002LVCMOS123.3Stratum 4E, SMC, ITU, Telcordia, Stratum 4, Stratum 3, GR-1244-CORE, ETS 300 011, ITU-T G.813 (Option 1), ITU-T G.812, TR62411No

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
82V3002APVGActivePVG56SSOP56CYesTubeCheck Availability
82V3002APVG8ActivePVG56SSOP56CYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL Application Note PDF 78 KB Apr 29, 2016
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
show all (13)
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-839 RMS Phase Jitter Application Note PDF 149 KB May 7, 2014
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 7, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 15, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
AN-406: WAN PLLs, FAQs Application Note PDF 60 KB Jul 17, 2003
PCN# : A1506-02 Gold wire to Copper wire Product Change Notice PDF 35 KB Oct 8, 2015
PDN# : CQ-13-01 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 302 KB Jul 25, 2013
PCN#: A-0410-02, Change IDT marking logo with new IDT gridless w Product Change Notice PDF 24 KB Nov 14, 2012
show all (10)
PCN# A-0508-02: OSET Alternate Assembly Location for Green Product Change Notice PDF 18 KB Sep 2, 2005
PCN#A-0504-02R1: Assembly Transfer IDT-Manila to OSE-Ph Product Change Notice PDF 16 KB Jul 22, 2005
PCN#: TB-0504-01, Transfer Test & Backend from IDT-Manila to IDT Product Change Notice PDF 35 KB Apr 29, 2005
PCN#: A-0504-02, Transfer assembly facility IDT-Manila to OSE-Ph Product Change Notice PDF 47 KB Apr 29, 2005
PCN#: A-0405-06, To qualify alternate facility ATP for PV (SSOP) Product Change Notice PDF 22 KB May 24, 2004
PCN # F0312: Datasheet Update Product Change Notice PDF 22 KB Dec 16, 2003
PCN# F0305-05: IDT82V300x Product Upgrade Product Change Notice PDF 50 KB May 23, 2003
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016