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82P33714 Functional Block Diagram
82P33714 Pin Diagram Top View

82P33714

Synchronous Equipment Timing Source for Synchronous Ethernet

The 82P33714 Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE) provides tools to manage timing references, clock generation and timing paths for SyncE based clocks, per ITU-T G.8264 and ITU-T G.8262. 82P33714 meets the requirements of ITU-T G.8262 for synchronous Ethernet Equipment Clocks (EECs) and ITU-T G.813 for Synchronous Equipment Clocks (SEC). The device outputs low-jitter clocks that can directly synchronize Ethernet interfaces; as well as SONET/SDH and PDH interfaces. For 10G-40G SyncE single-board applications, see the 82P33731

IDT’s third generation Universal Frequency Translator family also includes the 8T49N285 (2-in / 1-PLL / 8-out), 8T49N286 (4-in / 2-PLL / 8-out), and 8T49N287 (2-in / 2-PLL / 8-out), and the 8T49N242 (2-in / 1-PLL / 4-out).

► Download the Altera and IDT Synchronous Ethernet Solution for ITU-T G.8262 white paper

Features

  • Complies with ITU-T G.8262 for Synchronous Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equipment Clock (SEC), and Telcordia GR-253-CORE for Stratum 3 and SONET Minimum Clock (SMC)
  • DPLLs lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI/OBSAI and GNSS frequencies using fractional-N input dividers
  • Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive and non-revertive settings and other programmable settings
  • Prevents output frequency corruption due to a bad PHY reference by accepting Loss of Signal (LOS) inputs from PHYs that immediately disqualify a reference
  • DPLL1 can be configured as a DCO (Digitally Controlled Oscillator) to support IEEE 1588 based clock generation under external processor control
  • Supports network timing master applications by locking to 1 PPS (Pulse Per Second) references from GPS or other GNSS sources
  • Eases local oscillator sourcing by supporting any of eight common TCXO/OCXO frequencies for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz
  • Automatically loads configuration from an external EPROM after reset without processor intervention
  • 72 pin QFN package

Product Options

Orderable Part IDPart StatusPkg. CodeTemp. GradePb (Lead) FreeCarrier TypeSample & Buy
82P33714ANLGActiveNLG72P2CYesTrayCheck Availability
82P33714ANLG8ActiveNLG72P2CYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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82P33714 Datasheet Datasheet PDF 932 KB Apr 28, 2016
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82P33714 Short Form Datasheet Short Form Datasheet PDF 235 KB Apr 4, 2016
Apps Notes & White Papers
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AN-946 Using a 19.2MHz System Clock with 82P337xx/8xx/9xx Application Note PDF 165 KB Aug 23, 2016
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AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
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AN-901 How to Implement Master/Slave for SETS and SMU Devices on Timing Redundancy Designs Application Note PDF 475 KB Jul 5, 2016
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AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL Application Note PDF 78 KB Apr 29, 2016
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AN-865 8T49N285_6_7 Frequency Synchronization Compliance Report Application Note PDF 1.04 MB Oct 28, 2015
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ITU-T Profiles for IEEE 1588 White Paper PDF 1.17 MB Oct 23, 2015
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AN-893 8T49N241_2 Frequency Synchronization Compliance Report Application Note PDF 1.02 MB Jul 7, 2015
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AN-861 Recommended Crystals for IDT VCXO-based Synchronization PLLs Application Note PDF 215 KB Apr 21, 2015
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AN-871 Generating SyncE Line Cards Using IDT UFT3G Application Note PDF 688 KB Oct 31, 2014
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AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 7, 2014
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AN-839 RMS Phase Jitter Application Note PDF 149 KB May 7, 2014
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AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-801 Crystal-High Drive Level Application Note PDF 109 KB Jan 15, 2014
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AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 15, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCNs & PDNs
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PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
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PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
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PCN# : N1412-01 Die revision change 82P33814, 82P33831, 82P33714, 82P33731, 82P33810 Product Change Notice PDF 40 KB Jan 6, 2015
Other
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IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
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Timing Fabric for Communications Equipment Overview Overview PDF 263 KB Dec 10, 2015
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UFT SyncE Product Brief 简体中文, 日本語 Product Brief PDF 132 KB Dec 15, 2014

Software & Tools

Title Type Format File Size Datesort icon
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82P33714NLG BSDL Model - BSDL TXT 15 KB Jan 16, 2015
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82P33714A IBIS Model Model - IBIS ZIP 173 KB Dec 11, 2014
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82P33x14 Timing Commander Personality Software TCP 2.94 MB May 13, 2015
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Timing Commander Installer v1.7.3.3 Software ZIP 17.87 MB May 12, 2016