Dual Synchronous Ethernet Line Card PLL
The 82V3396 Dual Synchronous Ethernet Line Card PLL is used to synchronize line cards in Synchronous Ethernet and SONET/SDH equipment, and in wireless base stations. The two independent timing paths allow the device to simultaneously synchronize transmit interfaces with the selected system backplane clock, and provide a recovered clock from a selected receive interface to the system backplane.
The 82V3396 accepts up to 6 input references operating at common Ethernet, SONET/SDH and PDH frequencies as well as other frequencies. The references are continually monitored for loss of signal and for frequency offset per user programmed thresholds. The active reference for each of the two Digital PLLs (DPLLs) is determined by forced selection or by automatic selection based on user programmed priorities and locking allowances and based on the reference monitors.
The two 82V3396 timing paths are defined by independent DPLLs with embedded clock synthesizers. Both DPLLs support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode the DPLLs generate clocks based on the master clock alone. In Locked mode the DPLLs filter reference clock jitter with one of the following selectable bandwidths: 18 Hz, 35 Hz, 70 Hz or 560 Hz. In Locked mode the long-term DPLL frequency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode the DPLL uses frequency data acquired while in Locked mode to generate accurate frequencies for short periods.
The 82V3396 requires a 12.8 MHz master clock for its reference monitors and other digital circuitry. The frequency accuracy of the master clock determines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the master clock determines the frequency stability of the DPLLs in Free-Run mode and in Holdover mode.
The clocks synthesized by the 82V3396 DPLLs can be passed through one of the two independent jitter attenuating APLLs (for jitter sensitive applications). Any of the DPLL or APLL clocks can be routed through a mux to any of the six clock outputs via independent output dividers.
The 82V3396 accepts sync pulse inputs that are associated with input references; the sync pulses can have frequencies of 1 Hz, 2 kHz or 8 kHz. The device aligns its output sync pulses with the selected input sync pulse.
All 82V3396 read/write registers are accessed through a SPI/I2C microprocessor interface.
- Integrates 2 DPLLs; one can be used on the transmit path and the other on the receive path
- Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet (SyncE)
- Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-4) jitter generation requirements
- Provides node clocks for Cellular and WLL base-station (GSM and 3G networks)
- Provides clocks for 1 Gigabit and 10 Gigabit Ethernet applications
- Supports programmable DPLL bandwidth: 18 Hz, 35 Hz, 70 Hz and 560 Hz
- Provides OUT1~OUT6 output clock frequencies up to 644.53125 MHz
- Provides IN1~IN6 input clock frequencies cover from 2 kHz to 156.25 MHz
- Supports manual and automatic selected input clock switch
- Supports automatic hitless selected input clock switch on clock failure
- Provides a 2 kHz, 4 kHz, or 8 kHz frame sync input signal, and a 2 kHz or 8 kHz frame sync output signals
- Provides a 1PPS sync input signal and a 1PPS sync output signal
- Provides output clocks for BITS, GPS, 3G, GSM, etc.
- Supports master clock calibration
- Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE, ITU-T G.812, ITU-T G.8262. ITU-T G.813 and ITU-T G.783 recommendations
- I2C and Serial microprocessor interface modes
- IEEE 1149.1 JTAG Boundary Scan
|App Jitter Compliance||Core Voltage (V)||Input Freq (MHz)||Input Type||Inputs (#)||Output Freq Range (MHz)||Output Signaling||Output Type||Output Voltage (V)||Phase Jitter Max RMS (ps)|
|Stratum 4E, Stratum 4, SMC, ITU, Telcordia, Stratum 3||3.3||0.000001 - 625.000000||LVPECL, LVDS, LVCMOS, AMI||6||0.000001 - 644.531250||LVDS, LVCMOS, AMI, LVPECL||LVDS, LVCMOS, AMI, LVPECL||3.3|