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8V89316 Functional Diagram

8V89316

Ethernet PLL and IEEE 1588 Synthesizer

The IDT8V89316 is used to frequency synchronize equipment with an Ethernet connected reference; its integrated DCO (Digitally Controlled Oscillator) can be controlled by an external IEEE 1588 clock recovery servo to synthesize IEEE 1588-based clocks. The IDT8V89316 low jitter output clocks can be used to directly time Gigabit Ethernet PHYs and QSGMII devices.

Features

  • Digital PLL synchronizes with Ethernet connected synchronization sources
  • DPLL bandwidth is 1.2 Hz; DPLL holdover accuracy is 1.1X10-5 ppm
  • Input references are monitored for frequency offset and activity
  • DPLL holdover, free run and hitless reference switching can be forced by the host processor or can be automatically controlled by an internal state machine
  • Internal DCO has resolution of 0.01105 ppb and can be controlled by an external processor via I2C interface for IEEE 1588 clock generation
  • One Analog PLL for jitter attenuation
  • Jitter generation <0.65ps RMS (10 kHz to 20 MHz), meets jitter requirements of 1 GbE PHYs and QSGMII
  • IN1, IN2 and IN3 accept single ended reference clocks whose frequencies can be 25 MHz, 125 MHz or 156.25 MHz
  • OUT1 outputs a differential clock with frequency of 125 MHz or 156.25 MHz
  • OUT2 to OUT6 output differential clocks all with the same frequency of 125 MHz or 156.25 MHz
  • OUT7 outputs a free-running LVCMOS clock with frequency of 25 MHz

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeCore Voltage (V)Phase Jitter Typ RMS (ps)App Jitter Compliance
7LVCMOS, LVPECL25.000000 - 156.25000025.000000 - 156.2500003LVCMOS3.30.500QSGMII, 1000BASE-T, 1000BASE-X

Product Options

Orderable Part IDPart StatusPkg. CodeTemp. GradePb (Lead) FreeCarrier TypeSample & Buy
8V89316BAGActiveBAG196CYesTrayCheck Availability
8V89316BAG8ActiveBAG196CYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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8V89316 Datasheet Datasheet PDF 501 KB Aug 20, 2014
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8V89316 Short Form Datasheet Short Form Datasheet PDF 174 KB May 5, 2014
User Guides & Manuals
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82V391x / 8V893xx WAN PLL Device Families – Device Driver User's Guide Manual - User Reference PDF 232 KB May 1, 2014
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8V89316 API Reference Manual Manual - Software PDF 6 MB May 1, 2014
Apps Notes & White Papers
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AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
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AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 7, 2014
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AN-839 RMS Phase Jitter Application Note PDF 149 KB May 7, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 15, 2014
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AN-801 Crystal-High Drive Level Application Note PDF 109 KB Jan 15, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
Other
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IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
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Timing Fabric for Communications Equipment Overview Overview PDF 263 KB Dec 10, 2015

Software & Tools

Title Type Format File Size Datesort icon
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8V89316 BSDL File Model - BSDL TXT 15 KB May 26, 2013
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8V89316 IBIS File (zip) Model - IBIS ZIP 86 KB Apr 14, 2014
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8V89316 Device Driver Package Version 1.2 (source only, tarball) Software application/x-gzip 160 KB Sep 25, 2013
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8V89316 Device Driver Package Version 1.2 (source only, zip) Software ZIP 275 KB Sep 25, 2013