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5V41068A - Block Diagram
5V41068A - Pinout


2:1 PCIe GEN1/2/3 Clock Multiplexer

The 5V41068A is a 2:1 differential clock mux for PCI Express applications. It has very low additive jitter making it suitable for use in PCIe Gen2 and Gen3 systems. The 5V41068A selects between 1 of 2 differential HCSL inputs to drive a single differential HCSL output pair. The output can also be terminated to LVDS.


  • 1 – 0.7V current mode differential HCSL output pair
  • Low additive jitter
  • suitable for use in PCIe Gen2 and Gen3 systems
  • 16-pin TSSOP package
  • small board footprint
  • Outputs can be terminated to LVDS
  • can drive a wider variety of devices
  • OE control pin
  • greater system power management
  • Industrial temperature range available
  • supports demanding embedded applications
  • Additive cycle-to-cycle jitter <5 ps
  • Additive phase jitter (PCIe Gen3) <0.2ps
  • Operating frequency up to 200MHz

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
1LVDS, HCSL0.000000 - 200.0000000.000000 - 200.0000002HCSL13.30.1

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
5V41068APGGActivePGG16TSSOP16CYesTubeCheck Availability
5V41068APGG8ActivePGG16TSSOP16CYesReelCheck Availability
5V41068APGGIActivePGG16TSSOP16IYesTubeCheck Availability
5V41068APGGI8ActivePGG16TSSOP16IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
5V41068A Datasheet Datasheet PDF 189 KB Apr 6, 2016
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB May 13, 2014
show all (11)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Apr 14, 2016
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Feb 15, 2016
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
show all (6)
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
PCN# : A1403-03 Gold wire to Copper wire Product Change Notice PDF 42 KB Oct 15, 2014
PCN# : TB1403-01 Changed in Carrier Tape, Plastic Reel and Quantity per Reel on TSSOP-14, TSSOP-16 Product Change Notice PDF 663 KB Apr 8, 2014
IDT PCI Express Solutions Overview 简体中文, 日本語 Overview PDF 945 KB Aug 4, 2016
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

Software & Tools

Title Type Format File Size Datesort icon
5V41068A IBIS Model Model - IBIS ZIP 6 KB Jan 16, 2014

News & Additional Resources

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