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4-Output Small Form Factor PCIe Gen1-2-3 Buffer for Freescale Systems

The IDT6P61043 is a 4-output very low power buffer for 100MHz PCIe Gen1, Gen2 and Gen3 applications with integrated output terminations providing Zo=100Ω for Freescale Systems. The device has 4 output enables for clock management, and 3 selectable SMBus addresses.


  • Integrated terminations provide differential Zo=100Ω: reduced component count and board space
  • 1.8V operation: minimal power consumption
  • OE# pins: support DIF power management
  • HCSL compatible differential input: can be driven by common clock sources.
  • LP-HCSL differential clock outputs: reduced power and board space
  • Programmable Slew rate for each output: allows tuning for various line lengths.
  • Programmable output amplitude: allows tuning for various application environments.
  • Pin/software selectable PLL bandwidth and PLL Bypass: minimize phase jitter for each application
  • Outputs blocked until PLL is locked: clean system start-up
  • Software selectable 50MHz or 125MHz PLL operation: useful for Ethernet Applications
  • Configuration can be accomplished with strapping pins: SMBus interface not required for device control.
  • 3.3V tolerant SMBus interface works with legacy controllers.
  • Space saving 32-pin 5x5mm MLF: minimal board space
  • Selectable SMBus addresses: multiple devices can easily share an SMBus segment.

Product Specification

App Jitter ComplianceCore Voltage (V)Input Freq (MHz)Output Freq Range (MHz)Output Voltage (V)Power Consumption Typ (mW)
PCIe Gen2, PCIe Gen3, PCIe Gen11.830.000000 - 137.50000030.000000 - 137.5000000.865

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
6P61043NLGIPreviewNLG32VFQFPN32IYesTrayCheck Availability
6P61043NLGI8PreviewNLG32VFQFPN32IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
6P61043 Datasheet_Freescale Datasheet PDF 198 KB Jul 3, 2013
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB Dec 10, 2015
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
show all (11)
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

News & Additional Resources

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