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8v31012 - Block Diagram
8v31012 - Pin Assignment

8V31012

1-to-12, Differential HCSL Fanout Buffer

The 8V31012 is a 1-to-12 Differential HCSL Fanout Buffer. The 8V31012 is designed to translate any differential signal levels to differential HCSL output levels. An external reference resistor is used to set the value of the current supplied to an external load/termination resistor. The load resistor value is chosen to equal the value of the characteristic line impedance of 50Ω. The 8V31012 is characterized at an operating supply voltage of 3.3V. 

The differential HCSL outputs, accurate crossover voltage and duty cycle make the 8V31012 ideal for interfacing to PCI Express and FBDIMM applications.

Features

  • Twelve differential HCSL outputs
  • Translates any differential input signal (LVPECL, LVHSTL, LVDSHCSL) to HCSL levels without external bias networks
  • Maximum output frequency: 250MHz
  • Output skew: 265ps (typical)
  • VOH: 850mV (maximum)
  • Full 3.3V supply voltage
  • Available in lead-free (RoHS 6) package
  • -40°C to 85°C ambient operating temperature

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Divider ValueOutput Skew (ps)Additive Phase Jitter Typ RMS (ps)
12HCSL0.000000 - 250.0000000.000000 - 250.0000001HSTL, LVPECL, HCSL, LVDS13.33.313950.15

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8V31012NLGIActiveNLG48P1VFQFPN48IYesTrayCheck Availability
8V31012NLGI8ActiveNLG48P1VFQFPN48IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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8V31012 Final Data Sheet Datasheet PDF 449 KB Oct 27, 2015
Apps Notes & White Papers
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AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB May 13, 2014
show all (12)
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
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AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
Other
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IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
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IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 17, 2015
show all (4)
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High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 14, 2012

News & Additional Resources

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