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9DB1933 - Block Diagram
9DB1933 - Pinout


19-output Differential Buffer For PCIe Gen3

The 9DB1933 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1933 is driven by a differential SRC output pair from an IDT 932S421, 932SQ420, or equivalent, main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking.


  • 19 - 0.7 V current mode differential HCSL output pairs
  • 8 Selectable SMBus Addresses/Mulitple devices can share the same SMBus Segment
  • 11 dedicated and 3 group OE# pins/Hardware control of the outputs
  • PLL or bypass mode/PLL can dejitter incoming clock
  • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s
  • Spread spectrum compatible, tracks spreading input clock for low EMI
  • SMBus Interface, unused outputs can be disabled
  • Supports undriven differential outputs in Power Down mode for power management
  • Cycle-to-cycle jitter <50 ps
  • Output-to-output skew < 150 ps
  • PCIe Gen3 phase jitter < 1.0 ps RMS

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)
19HCSL10.000000 - 167.0000000.000000 - 100.0000001HCSL13.33.3

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
9DB1933AKLFActiveNLG72P1VFQFPN72CYesTrayCheck Availability
9DB1933AKLFTActiveNLG72P1VFQFPN72CYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
9DB1933 Datasheet Datasheet PDF 185 KB Dec 6, 2011
9DB1933 Datasheet Datasheet PDF 185 KB Nov 16, 2011
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB May 13, 2014
show all (10)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB Oct 22, 2015
show all (7)
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB Jul 21, 2015
PCN# : A1311-03R1 Alternate Assembly Locations Product Change Notice PDF 43 KB Feb 16, 2014
PCN# : A1311-03 Alternate Assembly Locations Product Change Notice PDF 140 KB Dec 3, 2013
PCN# : A1308-01 Add ASEK as Alternate Assembly for VFQFPN-72 Product Change Notice PDF 103 KB Aug 18, 2013
IDT PCI Express Solutions Overview 简体中文, 日本語 Overview PDF 945 KB Aug 4, 2016
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
show all (5)
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 17, 2015
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 14, 2012

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