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9DBU0941 PCIe Clock Buffer Block Diagram
9DBU0941 PCIe Clock Buffer Pin Diagram


9-output 1.5 V PCIe Gen1-2-3 Fanout Buffer with Zo=100 ohms

The 9DBU0941 is a member of IDT’s 1.5 V Ultra-Low-Power (ULP) PCIe family. It has integrated terminations for direct connection to 100 ohm transmission lines. The device has 9 output enables for clock management, and 3 selectable SMBus addresses.


  • Integrated terminations; save 36 resistors compared to standard HCSL outputs
  • 47 mW typical power consumption; minimal power consumption
  • OE# pin for each output; support DIF power management
  • HCSL differential input; can be driven by common clock sources
  • Spread spectrum tolerant; allows reduction of EMI
  • Programmable slew rate for each output; allows tuning for various line lengths
  • Programmable output amplitude; allows tuning for various application environments
  • 1 MHz to 167 MHz operating frequency
  • 3.3 V tolerant SMBus interface; works with legacy controllers
  • Selectable SMBus addresses; multiple devices can easily share an SMBus segment
  • Device contains default configuration; SMBus interface not required for device operation
  • Space-saving 6x6 mm 48-pin VFQFPN; minimal board space

Product Specification

App Jitter CompliancePLLDiff. OutputsDiff. Output SignalingOutput Banks (#)Diff. InputsDiff. Input SignalingPower Consumption Typ (mW)Supply Voltage (V)
PCIe Gen3, PCIe Gen2, PCIe Gen1No9LP-HCSL11HCSL561.05 - 1.50, 1.50

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
9DBU0941AKILFActiveNDG48P1VFQFPN48IYesTrayCheck Availability
9DBU0941AKILFTActiveNDG48P1VFQFPN48IYesReelCheck Availability
9DBU0941AKLFActiveNDG48P1VFQFPN48CYesTrayCheck Availability
9DBU0941AKLFTActiveNDG48P1VFQFPN48CYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
9DBU0941 Datasheet Datasheet PDF 299 KB Oct 28, 2015
Apps Notes & White Papers
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB Dec 10, 2015
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 150 KB Apr 8, 2015
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB May 13, 2014
show all (9)
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB Oct 22, 2015
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB Jul 21, 2015
IDT PCI Express Solutions Overview 简体中文, 日本語 Overview PDF 945 KB Aug 4, 2016
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
show all (5)
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 17, 2015
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 14, 2012

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