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9EX21531 - Block Diagram
9EX21531 - Pinout


Fifteen Output Differential Buffer W/2 Input MUX For PCIe GEN1/2/3

The 9EX21531 provides 15 output clocks for PCIe Gen1/ 2/3 applications. The 9EX21531 has 4 selectable SMBus addresses, and dedicated CKPWRGD/PD# and VDDA pins for easy board design. A differential clock from a CK410B+ or CK420BQ main clock generator, such as the 932S421, drives the 9EX21531. In fanout mode, the 9EX21531 provides outputs up to 166MHz.


  • 15 - 0.7V current mode differential HSCL output pairs
  • Pin compatible to 9EX21501/ Easy PCIe Gen3 upgrade
  • 4 Selectable SMBus Addresses/Mulitple devices can share the same SMBus Segment
  • 8 dedicated and 2 group OE# pins/Hardware control of the outputs
  • PLL or bypass mode/PLL can dejitter incoming clock
  • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s
  • Spread Spectrum Compatible/tracks spreading input clock for low EMI
  • SMBus Interface/unused outputs can be disabled
  • Undriven differential outputs in Power Down mode/ Easy power management
  • Cycle-to-cycle jitter <50ps
  • Output-to-output skew < 150 ps
  • PCIe Gen3 phase jitter < 1.0ps RMS

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)
15HCSL33.330000 - 167.0000000.000000 - 166.0000002HCSL13.30.8

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
9EX21531AKLFActiveNLG64P2VFQFPN64CYesTrayCheck Availability
9EX21531AKLFTActiveNLG64P2VFQFPN64CYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
9EX21531 Datasheet Datasheet PDF 221 KB Oct 25, 2016
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB May 13, 2014
show all (10)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB Oct 22, 2015
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB Jul 21, 2015
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

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