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9FGV0431 - Block Diagram


4-output 1.8 V PCIe Gen1-2-3 Clock Generator

The 9FGV0431 is a 4-output very low power clock generator for PCIe Gen 1, 2 and 3 applications. The device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.


  • 1.8 V operation: reduced power consumption
  • OE# pins: support DIF power management
  • LP-HCSL differential clock outputs: reduced power and board space
  • Programmable slew rate for each output: allows tuning for various line lengths
  • Programmable output amplitude: allows tuning for various application environments
  • DIF outputs blocked until PLL is locked: clean system start-up
  • Selectable 0%, -0.25% or -0.5% spread on DIF outputs: reduces EMI
  • External 25 MHz crystal; supports tight ppm with 0 ppm synthesis error
  • Configuration can be accomplished with strapping pins: SMBus interface not required for device control
  • 3.3 V tolerant SMBus interface works with legacy controllers
  • Space-saving 5x5 mm 32-pin VFQFPN; minimal board space
  • Selectable SMBus addresses: multiple devices can easily share an SMBus segment

Product Specification

App Jitter ComplianceCore Voltage (V)Input Freq (MHz)Output Freq Range (MHz)Output Voltage (V)Power Consumption Typ (mW)Spread Spectrum
PCIe Gen4, PCIe Gen3, PCIe Gen2, PCIe Gen11.825.00000025.000000, 100.0000000.8, 1.858Yes

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
9FGV0431AKILFActiveNLG32P3VFQFPN32IYesTrayCheck Availability
9FGV0431AKILFTActiveNLG32P3VFQFPN32IYesReelCheck Availability
9FGV0431AKLFActiveNLG32P3VFQFPN32CYesTrayCheck Availability
9FGV0431AKLFTActiveNLG32P3VFQFPN32CYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
9FGV0431 Datasheet Datasheet PDF 219 KB Oct 19, 2016
Apps Notes & White Papers
AN-918 Programmable Clocks vs Crystal Oscillators Application Note PDF 221 KB Mar 10, 2016
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB Dec 10, 2015
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 150 KB Apr 8, 2015
show all (13)
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-839 RMS Phase Jitter Application Note PDF 149 KB May 7, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB Mar 12, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
9FGV0431 Reference Schematic Schematic PDF 29 KB Jan 23, 2015

Software & Tools

Title Type Format File Size Datesort icon
9FGV0431 IBIS Model Model - IBIS ZIP 93 KB Dec 2, 2015

News & Additional Resources

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