4-output 1.8 V PCIe Gen1-2-3 Clock Generator with Zo=100 ohms

The 9FGV0441 is an 4-output very low power clock generator for PCIe Gen1-2-3 applications with integrated output terminations providing Zo=100 Ω. The device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.

Features

  • Integrated terminations provide 100 Ω differential Zo: reduced component count and board space
  • 1.8 V operation: reduced power consumption
  • OE# pins: support DIF power management
  • LP-HCSL differential clock outputs: reduced power and board space
  • Programmable slew rate for each output: allows tuning for various line lengths
  • Programmable output amplitude: allows tuning for various application environments
  • DIF outputs blocked until PLL is locked: clean system start-up
  • Selectable 0%, -0.25% or -0.5% spread on DIF outputs: reduces EMI
  • External 25MHz crystal; supports tight ppm with 0 ppm synthesis error
  • Configuration can be accomplished with strapping pins: SMBus interface not required for device control
  • 3.3 V tolerant SMBus interface works with legacy controllers
  • Space saving 5x5 mm 32-pin VFQFPN; minimal board space
  • Selectable SMBus addresses: multiple devices can easily share an SMBus segment

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9FGV0441AKILF Active NLG32P3 VFQFPN 32 I Yes Tray Availability
9FGV0441AKILFT Active NLG32P3 VFQFPN 32 I Yes Reel Availability
9FGV0441AKLF Active NLG32P3 VFQFPN 32 C Yes Tray Availability
9FGV0441AKLFT Active NLG32P3 VFQFPN 32 C Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
9FGV0441 Datasheet - Datasheet PDF 224 KB Oct 19, 2016
User Guides & Manuals
Timing Products for Freescale i.MX 简体中文 Guide PDF 390 KB Jan 11, 2016
Application Notes & White Papers
AN-835 Differential Input with VCMR being VIH Referenced - Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units - Application Note PDF 476 KB Apr 23, 2014
AN-918 Programmable Clocks vs Crystal Oscillators - Application Note PDF 221 KB Mar 9, 2016
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs - Application Note PDF 354 KB Dec 10, 2015
AN-879 Low-Power HCSL vs Traditional HCSL - Application Note PDF 150 KB Apr 7, 2015
AN-843 PCI Express Reference Clock Requirements - Application Note PDF 1.81 MB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection - Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals - Application Note PDF 349 KB May 7, 2014
AN-839 RMS Phase Jitter - Application Note PDF 149 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels - Application Note PDF 37 KB May 5, 2014
AN-802 Crystal-Measuring Oscillator Negative Resistance - Application Note PDF 52 KB Mar 11, 2014
AN-827 Application Relevance of Clock Jitter - Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads - Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location - Product Change Notice PDF 583 KB Dec 19, 2016
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location - Product Change Notice PDF 596 KB Jan 27, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location - Product Change Notice PDF 544 KB Nov 12, 2015
Other
The IDT Communications Products Advantage - Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016
Automotive Solutions Overview 简体中文 Overview PDF 2.79 MB Mar 8, 2016

Software & Tools

Title Other Languages Type Format File Size Date
9FGV0441 IBIS Model - Model - IBIS ZIP 97 KB Dec 2, 2015