Skip to main content
8P34S1208i Block Diagram
8P34S1208i Pinout

8P34S1208i

1:8 LVDS Output 1.8V Fanout Buffer

The IDT 8P34S1208i is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8P34S1208i is characterized to operate from a 1.8V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S1208i ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low skew
outputs are available. The integrated bias voltage reference enables easy interfacing of AC-coupled signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Features

  • Eight low skew, low additive jitter LVDS output pairs
  • Two selectable, differential clock input pairs
  • Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL, CML
  • Maximum input clock frequency: 1.2GHz (maximum)
  • LVCMOS/LVTTL interface levels for the control input select pin
  • Output skew: 20ps (typical)
  • Propagation delay: 315ps (typical)
  • Low additive phase jitter, RMS
  • fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz: 41fs (typical)
  • Full 1.8V supply voltage
  • Lead-free (RoHS 6), 28-Lead VFQFN packaging
  • -40°C to 85°C ambient operating temperature

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
8LVDS0.000000 - 1200.0000000.000000 - 1200.0000002LVDS, CML, LVPECL11.81.8200.041

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8P34S1208NBGIActiveNBG28VFQFPN28IYesTrayCheck Availability
8P34S1208NBGI8ActiveNBG28VFQFPN28IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
no-lock
IDT8P34S1208I Datasheet Datasheet PDF 339 KB Jan 24, 2014
Apps Notes & White Papers
no-lock
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
no-lock
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
no-lock
AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
show all (12)
no-lock
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
no-lock
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
no-lock
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
no-lock
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
no-lock
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
no-lock
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
no-lock
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
no-lock
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
no-lock
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
Other
no-lock
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

Related Videos

  • 2014-01-30 1.8V LVDS Clock Buffers by IDT: Low-power,...