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8P34S2106 - Block Diagram
8P34S2106 - Pin Assignment

8P34S2106

Dual 1:6 LVDS Output 1.8V Fanout Buffer

The 8P34S2106 is a high-performance, low-power, differential dual 1:6 LVDS output 1.8V fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. Two independent buffer channels are available, each channel has six low-skew outputs. High isolation between channels minimizes noise coupling. AC characteristics such as propagation delay are matched between channels. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S2106 ideal for clock distribution applications demanding well-defined performance and repeatability. The device is characterized to operate from a 1.8V power supply. The integrated bias voltage references enable easy interfacing of AC-coupled signals to the device inputs.

Features

  • Dual 1:6 low skew, low additive jitter LVDS fanout buffers
  • Matched AC characteristics across both channels
  • High isolation between channels
  • Low power consumption
  • Both differential CLKA, nCLKA and CLKB, nCLKB inputs accept
    LVDS, LVPECL and single-ended LVCMOS levels
  • Maximum input clock frequency: 2GHz
  • Output amplitudes: 350mV, 500mV (selectable)
  • Output bank skew: 10ps typical
  • Output skew: 20ps typical
  • Low additive phase jitter, RMS: <45fs typical,
    (fREF = 156.25MHz, 12kHz - 20MHz)
  • Full 1.8V supply voltage mode
  • Lead-free (RoHS 6), 40-lead VFQFN packaging
  • -40°C to 85°C ambient operating temperature
  • Supports case temperature up to 105°C
 

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
12LVDS0.000000 - 2000.0000000.000000 - 2000.0000002LVPECL, LVDS, LVCMOS21.81.8400.045

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradeTape Pin 1 QuadPb (Lead) FreeCarrier TypeSample & Buy
8P34S2106NLGIActiveNLG40P2VFQFPN40I1YesTrayCheck Availability
8P34S2106NLGI/WActiveNLG40P2VFQFPN40I1YesReelCheck Availability
8P34S2106NLGI8ActiveNLG40P2VFQFPN40I1YesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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8P34S2106 Datasheet Datasheet PDF 361 KB Jul 28, 2016
Apps Notes & White Papers
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AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (11)
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
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AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
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AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
Other
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

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