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8SLVD1208-33I

1:8, LVDS Output Fanout Buffer

The IDT8SLVD1208-33I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8SLVD1208-33I is characterized to operate from a 3.3V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8SLVD1208-33I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
 
For a 2.5 V version of this device, please refer to the 8SLVD1208I

Features

  • Eight low skew, low additive jitter LVDS output pairs
  • Two selectable, differential clock input pairs
  • Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL
  • Maximum input clock frequency: 2GHz (maximum)
  • LVCMOS/LVTTL interface levels for the control select input
  • Output skew: 8ps (typical)
  • Propagation delay: 240ps (typical)
  • Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10kHz - 20MHz: 82fs (typical)
  • Maximum device current consumption (IDD): 190mA (maximum) @ 3.465V
  • 3.3V supply voltage
  • Lead-free (RoHS 6), 28-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
8LVDS0.000000 - 2000.0000000.000000 - 2000.0000002LVDS, LVPECL13.3200.082

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8SLVD1208-33NBGIActiveNBG28VFQFPN28IYesTrayCheck Availability
8SLVD1208-33NBGI8ActiveNBG28VFQFPN28IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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IDT8SLVD1208-33I Datasheet Datasheet PDF 394 KB Feb 12, 2014
Apps Notes & White Papers
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (10)
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
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AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
Other
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
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IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 17, 2015
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High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 14, 2012

Software & Tools

Title Type Format File Size Datesort icon
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8SLVD1208-33I IBIS Model Model - IBIS ZIP 35 KB Oct 20, 2015

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