Skip to main content

8SLVD1212

1:12, LVDS Output Fanout Buffer

The 8SLVD1212 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD1212 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD1212 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Features

  • Twelve low skew, low additive jitter LVDS output pairs
  • Two selectable, differential clock input pairs
  • Differential PCLK, nPCLK pairs can accept the following differential
    input levels: LVDS, LVPECLCML
  • Maximum input clock frequency: 2GHz (maximum)
  • LVCMOS/LVTTL interface levels for the control input select pins
  • Output skew: 45ps (max)
  • Propagation delay: 310ps (typical)
  • Low additive phase jitter, RMS; fREF = 156.25MHz,
    10kHz - 20MHz: 77fs (typical)
  • Maximum device current consumption (IDD): 213mA
  • 2.5V supply voltage
  • Lead-free (RoHS 6), 40-Lead VFQFN packaging
  • -40°C to 85°C ambient operating temperature

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
12LVDS0.000000 - 2000.0000000.000000 - 2000.0000002LVPECL, LVDS, CML12.5450.065

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8SLVD1212NLGIActiveNLG40P2VFQFPN40IYesTrayCheck Availability
8SLVD1212NLGI/WActiveNLG40P2VFQFPN40IYesReelCheck Availability
8SLVD1212NLGI8ActiveNLG40P2VFQFPN40IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
no-lock
8SLVD1212 Datasheet Datasheet PDF 549 KB Jul 5, 2016
Apps Notes & White Papers
no-lock
AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
no-lock
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
no-lock
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (10)
no-lock
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
no-lock
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
no-lock
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
no-lock
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
no-lock
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
no-lock
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
no-lock
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
Other
no-lock
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
no-lock
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 17, 2015
no-lock
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 14, 2012