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8SLVP2108I - Block Diagram
8SLVP2108I - Pinout


Dual 1:8, 3.3V, 2.5V LVPECL Output Fanout Buffer


The IDT8SLVP2108I is a high-performance differential dual 1:8 LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8SLVP2108I is characterized to operate from a 3.3V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8SLVP2108I ideal for those clock distribution applications demanding well-defined  performance and repeatability. Two independent buffers with eight low skew outputs each are available. The integrated bias voltage references enable easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.


  • Two 1:8, low skew, low additive jitter LVPECL fanout buffers
  • Two differential clock inputs
  • Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can accept the following differential input levels: LVDS, LVPECL, CML
  • Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also accept single-ended LVCMOS levels.
  • Maximum input clock frequency: 2GHz
  • Output bank skew: 15ps (typical)
  • Propagation delay: 390ps (maximum)
  • Low additive phase jitter, RMS: 54fs (maximum) (fREF = 156.25MHz, VPP = 1V, 12kHz – 20MHz, VCC = 3.3V)
  • Full 3.3V and 2.5V supply voltage
  • Maximum device current consumption (IEE): 143mA
  • Available in Lead-free (RoHS 6), 48-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
16LVPECL0.000000 - 2000.0000000.000000 - 2000.0000002LVPECL22.5, 3.32.5, 3.3250.043

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8SLVP2108ANLGIActiveNLG48P1VFQFPN48IYesTrayCheck Availability
8SLVP2108ANLGI/WActiveNLG48P1VFQFPN48IYesReelCheck Availability
8SLVP2108ANLGI8ActiveNLG48P1VFQFPN48IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
IDT8SLVP2108I Datasheet PDF 961 KB May 21, 2014
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (10)
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1403-03 Gold wire to Copper wire Product Change Notice PDF 42 KB Oct 15, 2014
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

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