LvHSTL to CMOS Clock Divider
The 558-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider (divide by 3, divide by 4). The four outputs are split into two banks of two outputs. Each bank has a separate output enable to tri-state the output buffers. The 558-02 is a member of the ICS Clock BlocksTM family of clock generation, synchronization, and distribution devices.
- 16-pin TSSOP package
- LVHSTL inputs
- Accepts up to 250 MHz input frequency
- Four low skew (<250 ps) outputs
- Selectable internal divider of 3 or 4
- Operating voltage of 3.3 V