Skip to main content
6T39007A - Block Diagram
6T39007A - Pinout


Clock Distribution Circuit

The IDT6T39007A is a low-power, four output clock distribution circuit. The device takes a TCXO or 1.8 V to 2.5 V LVCMOS input and generates four high-quality LVDS outputs, and two programmable divided outputs. It includes a redundant input with automatic glitch-free switching when the primary reference is removed. The primary input may be selected by the user by pulling the SEL pin low or high. If the primary input is removed and brought back, it will not be re-selected until 1024 cycles have passed. The IDT6T39007A specifically addresses the needs of handheld applications in both performance and package size. The device is packaged in a small 4mm x 4mm 24-pin QFN, allowing optimal use for limited board space.


  • Packaged in 24-pin QFN
  • TCXO sine wave input
  • +2.5 V operating voltage
  • Four buffered LVDS outputs
  • Two programmable outputs for power control up to 3.0 V LVCMOS levels based on VDDO1/VDDO2
  • Individual output enables controlled via I2C or OEx
  • Pb-free, RoHS compliant package
  • Industrial temperature range (-40°C to +85°C)

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Divider ValueOutput Skew (ps)Additive Phase Jitter Typ RMS (ps)
6LVCMOS, LVDS12.600000 - 13.40000012.600000 - 13.4000002Sine Wave, LVCMOS22.5315, 46

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
6T39007ANLGIActiveNLG24P1VFQFPN24IYesTubeCheck Availability
6T39007ANLGI8ActiveNLG24P1VFQFPN24IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
6T39007A Datasheet Datasheet PDF 132 KB Feb 22, 2012
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
show all (10)
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1403-03 Gold wire to Copper wire Product Change Notice PDF 42 KB Oct 15, 2014
PCN# W1002-01(R4) Product Change Notice PDF 377 KB Oct 5, 2010
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 17, 2015
show all (4)
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 14, 2012