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85102I - Block Diagram
85102I - Pinout


Low Skew,1-to-2 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer

The 85102I is a low skew, high performance 1-to-2 Differential-to-HCSL fanout buffer. The 85102I has a differential clock input. The CLK0, nCLK0 input pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/deassertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the 85102I ideal for those applications demanding well defined performance and repeatability.


  • Two 0.7V differential HCSL outputs
  • Selectable differential CLK0, nCLK0 or LVCMOS inputs
  • CLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTLHCSL
  • CLK1 can accept the following input levels: LVCMOS or LVTTL
  • Maximum output frequency: 500MHz
  • Translates any single-ended input signal to 3.3V HCSL levels with resistor bias on nCLK input
  • Output skew: 65ps (maximum)
  • Part-to-part skew: 600ps (maximum)
  • Propagation delay: 3.2ns (maximum)
  • Additive phase jitter, RMS: 0.14ps typical @ 250MHz
  • 3.3V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
2HCSL0.000000 - 500.0000000.000000 - 500.0000002HSTL, LVCMOS, LVDS, LVPECL, HCSL13.3650.14

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
85102AGILFActivePGG16TSSOP16IYesTubeCheck Availability
85102AGILFTActivePGG16TSSOP16IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
85102i Datasheet Datasheet PDF 240 KB Dec 19, 2014
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (11)
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Apr 14, 2016
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Feb 15, 2016
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
show all (6)
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
PCN# : TB1403-01 Changed in Carrier Tape, Plastic Reel and Quantity per Reel on TSSOP-14, TSSOP-16 Product Change Notice PDF 663 KB Apr 8, 2014
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 24, 2013
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 17, 2015

Software & Tools

Title Type Format File Size Datesort icon
85102i IBIS Model Model - IBIS ZIP 43 KB Nov 26, 2009