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8530 - Block Diagram
8530 - Pinout


Low Skew,1-to-16,Differential-to-2.5V LVPECL Fanout Buffer

The 8530 is a low skew, 1-to-16 Differential-to- 2.5V LVPECL Fanout Buffer. The CLK, nCLK pair can accept most standard differential input levels. The high gain differential amplifier accepts peak-to-peak input voltages as small as 150mV, as long as the common mode voltage is within the specified minimum and maximum range. Guaranteed output and part-to-part skew characteristics make the 8530 ideal for those clock distribution applications demanding well defined performance and repeatability.


  • Sixteen differential LVPECL output pairs
  • CLK, nCLK input pair
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSLSSTL
  • Maximum output frequency: 500MHz
  • Translates any single-ended input signal to 2.5V LVPECL levels with a resistor bias on nCLK input
  • Output skew: 50ps (maximum)
  • Part-to-part skew: 250ps (maximum)
  • Propagation delay: 2ns (maximum)
  • 3.3V core, 2.5V output operating supply
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Divider ValueOutput Skew (ps)Additive Phase Jitter Typ RMS (ps)
16LVPECL0.000000 - 500.0000000.000000 - 500.0000001HCSL, SSTL, HSTL, LVDS, LVPECL13.32.550

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8530DYLFActivePRG48TQFP48CYesTrayCheck Availability
8530DYLF/WActivePRG48TQFP48CYesReelCheck Availability
8530DYLFTActivePRG48TQFP48CYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
8530 Datasheet Datasheet PDF 301 KB Jun 26, 2015
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (11)
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Apr 14, 2016
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Feb 15, 2016
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB Oct 22, 2015
show all (6)
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB Jul 21, 2015
PCN# : TB1303-01 Change of Carrier Tape for TQFP-32, TQFP-48 Product Change Notice PDF 472 KB Mar 31, 2013
PCN# : N1110-01 CHANGE OF DATASHEET AND TEST PROGRAM 8530DYLF, 8530DYLFT Product Change Notice PDF 72 KB Oct 25, 2011
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

Software & Tools

Title Type Format File Size Datesort icon
8530 IBIS Model Model - IBIS ZIP 6 KB Nov 10, 2009