Skip to main content

853S004I

Low Skew,1-to-4 Differential-to-2.5V, 3.3V LVPECL Fanout Buffer

The ICS853S004I is a low skew, high performance 1-to-4, 2.5V/3.3V Differential-to-LVPECL Fanout Buffer. Guaranteed output and part-to-part skew characteristics make the ICS853S004I ideal for those applications demanding well defined performance and repeatability.

Features

  • Four differential LVPECL outputs
  • Differential LVPECL clock input pair
  • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML
  • Maximum output frequency: 2GHz
  • Output skew: 25ps (maximum)
  • Part-to-part skew: 100ps (maximum)
  • Propagation delay: 500ps (maximum)
  • Additive Phase Jitter, RMS: 0.10ps (maximum) @156.25MHz (12kHz - 20MHz)
  • Clock enable signal synchronized to eliminate runt clock pulses
  • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V
  • -40°C to 85°C ambient operating temperature

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
4LVPECL0.000000 - 2000.0000000.000000 - 2000.0000001LVDS, LVPECL, CML12.5, 3.3250.07

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
853S004AKILFActiveNLG16VFQFPN16IYesTubeCheck Availability
853S004AKILFTActiveNLG16VFQFPN16IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
no-lock
ICS853S004I Datasheet Datasheet PDF 233 KB Aug 6, 2013
Apps Notes & White Papers
no-lock
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
no-lock
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
no-lock
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (11)
no-lock
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
no-lock
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
no-lock
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
no-lock
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
no-lock
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
no-lock
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
no-lock
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
no-lock
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCNs & PDNs
no-lock
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
no-lock
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
Other
no-lock
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
no-lock
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
no-lock
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 17, 2015
show all (4)
no-lock
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 14, 2012