Low Skew,1-to-24,Differential-to-3.3V,2.5V LVPECL Fanout Buffer

The 853S024 is a low skew, 1-to-24 Differential-to-3.3V, 2.5V LVPECL Fanout Buffer. The PCLK, nPCLK pair can accept most standard differential input levels. The 853S024 is characterized to operate from either a 3.3V or a 2.5V power supply. Guaranteed output skew characteristics make the 853S024 ideal for those clock distribution applications demanding well defined performance and repeatability.

Features

  • Twenty four LVPECL outputs.
  • One differential clock input pair
  • Differential input clock (PCLK, nPCLK) can accept the following signaling levels: LVDS, LVPECL, CML
  • Maximum output frequency: 2GHz
  • Translates any single ended input signal to 3.3V, 2.5V LVPECL levels with resistor bias on nPCLK input
  • Output skew: 125ps (maximum)
  • Rise and Fall Time: 180ps (typical)
  • Additive phase jitter, RMS: 0.15ps (typical) @ 156.25MHz
  • Full 3.3V or 2.5V supply voltage
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
853S024AYLF Active EDG64P2 TQFP 64 C Yes Tray Availability
853S024AYLFT Active EDG64P2 TQFP 64 C Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
ICS853S024 Datasheet - Datasheet PDF 798 KB Jul 24, 2011
Application Notes & White Papers
AN-835 Differential Input with VCMR being VIH Referenced - Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units - Application Note PDF 476 KB Apr 23, 2014
AN-828 Termination - LVPECL - Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers - Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection - Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals - Application Note PDF 349 KB May 7, 2014
AN-836 Differential Input to Accept Single-ended Levels - Application Note PDF 37 KB May 5, 2014
AN-834 Hot-Swap Recommendations - Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention - Application Note PDF 94 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter - Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads - Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PCN# : A1606-02 Add Greatek Taiwan as Alternate Assembly - Product Change Notice PDF 567 KB Aug 25, 2016
PCN# : A1402-02 Alternate Assembly Locations - Product Change Notice PDF 34 KB Sep 27, 2014
PCN# : TB1405-01 New Carrier Tape and Quantity per Reel - Product Change Notice PDF 788 KB Jul 6, 2014
Other
The IDT Communications Products Advantage - Overview PDF 2.54 MB Feb 13, 2017
The IDT Consumer Products Advantage - Overview PDF 6.67 MB Jan 27, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
The IDT Automotive Advantage - Overview PDF 5.67 MB Jan 18, 2017
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

Software & Tools

Title Other Languages Type Format File Size Date
853S024 IBIS Model - Model - IBIS ZIP 10 KB Jul 1, 2008