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853S54I - Block Diagram
853S54I - Pinout


Dual 2:1,1:2 Differential-to-LVPECL/ECL Multiplexer

The 853S54I is a dual 2:1 and 1:2 Multiplexer. The 2:1 Multiplexer allows one of 2 inputs to be selected onto one output pin and the 1:2 MUX switches one input to one of two outputs. This device is useful for multiplexing multi-rate Ethernet PHYs which have 100 M bit and 1000 bit transmit/receive pairs onto an optical SFP module which has a single transmit/receive pair. See Application Section for further information. The 853S54I is optimized for applications requiring very high performance and has a maximum operating frequency of 2.5GHz. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards.


  • Three differential LVPECL output pairs
  • Three differential LVPECL clock inputs
  • PCLKx/nPCLKx pairs can accept the following differential input levels: LVPECLLVDS
  • Maximum output frequency: 2.5GHz
  • Part-to-part skew: 200ps (maximum)
  • Propagation delay: QA, nQA: 450ps (maximum) QBx, nQBx: 420ps (maximum)
  • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V
  • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.465V to -2.375V
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
3LVPECL0.000000 - 2500.0000000.000000 - 2500.0000003LVPECL, LVDS32.5, 3.30.035

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
853S54AKILFActiveNLG16VFQFPN16IYesTubeCheck Availability
853S54AKILFTActiveNLG16VFQFPN16IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
853S54I Datasheet Datasheet PDF 472 KB Apr 11, 2014
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (11)
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

Software & Tools

Title Type Format File Size Datesort icon
853s54I IBIS Model Model - IBIS ZIP 73 KB May 27, 2010