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853S9252I - Block Diagram
853S9252I - Pinout


2.5V,3.3V ECL/LVPECL Clock /Data Fanout Buffer

The 853S9252I is a 2.5V/3.3V ECL/LVPECL fanout buffer designed for high-speed, low phase-noise wireless infrastructure applications. The device fanouts a differential input signal to two ECL/LVPECL outputs. Optimized for low additive phase-noise, sub-100ps output rise and fall times, low output skew and high-frequencies, the 853S9252I is an effective solution for high-performance clock and data distribution applications, for instance driving the reference clock inputs of ADC/DAC circuits. Internal input termination, a bias voltage output (VREF) for AC-coupling and small packaging (3.0mm x 3.0mm 16-lead VFQFN) supports space-efficient board designs. The 853S9252I operates from a full 2.5V or 3.3V power supply and supports the industrial temperature range of -40°C to 85°C. The extended temperature range also supports wireless infrastructure, tele-communication and networking end equipment requirements.


  • 1:2 differential clock/data fanout buffer
  • Clock frequency: 3GHz (maximum)
  • Two differential 2.5V/3.3V ECL/LVPECL clock output
  • Differential input accepts ECL/LVPECL, LVDS and CML levels
  • Additive phase jitter, RMS @ 122.88MHz: 45fs (typical)
  • Propagation delay: 175ps (maximum), VCC = 3.3V
  • Output rise/fall time: 135ps (maximum), VCC = 3.3V
  • Internal input signal termination
  • Supply voltage: 2.5V-5% to 3.3V+10%
  • Available in Lead-free (RoHS 6) package
  • -40°C to 85°C ambient operating temperature

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Divider ValueOutput Skew (ps)Additive Phase Jitter Typ RMS (ps)
2LVPECL0.000000 - 3000.0000000.000000 - 3000.0000001LVDS, LVPECL, CML12.5, 3.32.5, 3.3170.045

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
853S9252BKILFActiveNLG16VFQFPN16IYesTubeCheck Availability
853S9252BKILFTActiveNLG16VFQFPN16IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
ICS853S9252I Datasheet Datasheet PDF 717 KB Jul 18, 2013
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (11)
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
PCN# : A1403-03 Gold wire to Copper wire Product Change Notice PDF 42 KB Oct 15, 2014
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016