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859S0212I - Block Diagram
859S0212I - Pinout


2:2 Differential-to-LVPECL/LVDS Clock Multiplexer

The 859S0212I is a 2:2 Differential-to-LVPECL/ LVDS Clock Multiplexer which can operate up to 3GHz. The 859S0212I has 2 selectable differential PCLKx, nPCLKx clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The clock select pin has an internal pulldown resistor.


  • High speed 2:1 differential multiplexer with a 1:2 fanout buffer
  • Two differential LVPECL or LVDS output pairs
  • Two selectable differential PCLKx, nPCLKx input pairs
  • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CMLSSTL
  • Maximum output frequency: 3GHz
  • Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input
  • Part-to-part skew: 25ps (typical)
  • Propagation delay: 555ps (typical)
  • Additive phase jitter, RMS: 0.16ps (typical)
  • Full 3.3V or 2.5V supply modes
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
2LVPECL, LVDS0.000000 - 3000.0000000.000000 - 3000.0000002LVDS, LVPECL, SSTL, CML12.5, 3.3250.021

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
859S0212BGILFActivePGG16TSSOP16IYesTubeCheck Availability
859S0212BGILFTActivePGG16TSSOP16IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
859S0212I Final Data Sheet Datasheet PDF 662 KB Jun 4, 2012
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
show all (12)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Apr 14, 2016
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Feb 15, 2016
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
show all (7)
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
PCN# : TB1403-01 Changed in Carrier Tape, Plastic Reel and Quantity per Reel on TSSOP-14, TSSOP-16 Product Change Notice PDF 663 KB Apr 8, 2014
PCN# : A1309-01 Changed of Traceability Mark Format Product Change Notice PDF 439 KB Oct 11, 2013
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 24, 2013
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

Software & Tools

Title Type Format File Size Datesort icon
859S0212I IBIS Model Model - IBIS ZIP 142 KB Nov 25, 2014