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870S208 - Block Diagram
870S208 - Pinout


Differential-to-LVCMOS/LVTTL Fanout Buffer W/Divider And Glitchless Switch

The 870S208 is a low skew, 8 output LVCMOS / LVTTL Fanout Buffer with selectable divider. The 870S208 has 2 selectable inputs that accept a variety of differential input types. The device provides the capability to suppress any glitch at the outputs of the device during an input clock switch to enhance clock redundancy in fault tolerant applications. The low impedance LVCMOS outputs are designed to drive 50? series or parallel terminated transmission lines. The effective fanout can be increased from 8 to 16 by utilizing the ability of the outputs to drive two series terminated lines. The divide select inputs, DIV_SELA and DIV_SELB, control the output frequency of each bank. The output banks can be independently selected for ÷1 or ÷2 operation. The output enable pins assigned to each output, support enabling and disabling of each output individually. The 870S208 is characterized at full 3.3V and 2.5V, and mixed 3.3V/2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the 870S208 ideal for high performance, single ended applications.


  • Eight LVCMOS/LVTTL outputs, (2 banks of 4 outputs) Each output has individual synchronous output enable
  • Two selectable differential CLKx, nCLKx inputs
  • Dual differential input pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTLHCSL
  • Maximum output frequency: 250MHz
  • Selectable ÷1 or ÷2 operation
  • Glitchless output behavior during input switch
  • Output skew: 50ps (typical), 3.3V
  • Bank skew: 30ps (typical), 3.3V
  • Supply modes: Core/Output 3.3V/3.3V 2.5V/2.5V 3.3V/2.5V
  • 0°C to 70°C ambient operating temperature
  • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Divider ValueOutput Skew (ps)Additive Phase Jitter Typ RMS (ps)
8LVCMOS0.000000 - 250.0000000.000000 - 250.0000002SSTL, LVPECL, LVDS, HSTL, HCSL22.5, 3.32.5, 3.31, 250

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
870S208BKLFActiveNLG32P3VFQFPN32CYesTrayCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
ICS870S208 Datasheet Datasheet PDF 211 KB Sep 12, 2013
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
show all (12)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016