2.5V Differential Clock Divider/Buffer

The 874328I-01 is a high-performance differential ÷1 and ÷4 clock divider and fanout buffer. The device is designed for the frequency-division and signal fanout of high-frequency, low phase-noise clock signals. The differential input signal is frequency divided by ÷1 and ÷4. Three LVPECL and three LVDS output banks are provided with a total of twenty differential outputs. The 874328I-01 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 874328I-01 ideal for those clock distribution applications demanding well-defined performance and repeatability.

Features

  • One differential input LVPECL reference clock
  • Differential pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
  • Integrated input termination resistors
  • One bank of three LVPECL outputs (÷1 frequency-divided)
  • One bank of three LVPECL outputs (÷4 frequency-divided)
  • One bank of two LVPECL outputs (÷4 frequency-divided)
  • Two banks of three LVDS outputs (÷4 frequency-divided)
  • One bank of six LVDS outputs (÷4 frequency-divided)
  • Total of twenty differential clock outputs
  • Maximum input frequency: 650MHz
  • Maximum output frequency: 650MHz (÷1 outputs)
  • Maximum output frequency: 162.5MHz (÷4 outputs)
  • LVCMOS interface levels for all control inputs
  • Output skew: 70ps (maximum)
  • Part-to-part skew: 250ps (maximum)
  • Full 2.5V supply voltage
  • Available in lead-free (RoHS 6) package
  • -40°C to 85°C ambient operating temperature

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
874328BYI-01LF Active EDG64P2 TQFP 64 I Yes Tray Availability
874328BYI-01LFT Active EDG64P2 TQFP 64 I Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
874328I-01 Data Sheet - Datasheet PDF 365 KB Jan 26, 2016
Application Notes & White Papers
AN-835 Differential Input with VCMR being VIH Referenced - Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units - Application Note PDF 476 KB Apr 23, 2014
AN-828 Termination - LVPECL - Application Note PDF 229 KB Jul 5, 2016
AN-846 Termination - LVDS - Application Note PDF 50 KB May 12, 2014
AN-844 Termination - AC Coupling Clock Receivers - Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection - Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals - Application Note PDF 349 KB May 7, 2014
AN-836 Differential Input to Accept Single-ended Levels - Application Note PDF 37 KB May 5, 2014
AN-834 Hot-Swap Recommendations - Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention - Application Note PDF 94 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter - Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads - Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PCN# : A1606-02 Add Greatek Taiwan as Alternate Assembly - Product Change Notice PDF 567 KB Aug 25, 2016
PCN# : A1402-02 Alternate Assembly Locations - Product Change Notice PDF 34 KB Sep 27, 2014
PCN# : TB1405-01 New Carrier Tape and Quantity per Reel - Product Change Notice PDF 788 KB Jul 6, 2014
Other
The IDT Communications Products Advantage - Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Products for Radio Applications 日本語 Product Brief PDF 2.34 MB Nov 29, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

Software & Tools

Title Other Languages Type Format File Size Date
ICS874328I-01 IBIS Model - Model - IBIS ZIP 68 KB Mar 15, 2011