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889474 - Block Diagram
889474 - Pinout


2:1 LVDS Multiplexer With 1:2 Fanout And Internal Termination

The 889474 is a high speed 2-to-1 differential multiplexer with integrated 2 output LVDS fanout buffer and internal termination and is a member of the family of high performance clock solutions from IDT. The 889474 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pins allow other differential signal families such as LVPECL, LVDS, LVHSTL and CML to be easily interfaced to the input with minimal use of external components. The 889474 is packaged in a small 4mm x 4mm 24-pin VFQFN package which makes it ideal for use in space-constrained applications.


  • Two differential LVDS outputs
  • INx, nINx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTLCML
  • 50? internal input termination to VT
  • Maximum output frequency: 2GHz (maximum)
  • Additive phase jitter, RMS: 0.06ps (typical)
  • Output skew: 20ps (maximum)
  • Propagation delay: 700ps (maximum)
  • 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free RoHS-complaint package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
2LVDS0.000000 - 2000.0000000.000000 - 2000.0000002HSTL, LVDS, LVPECL, CML12.5200.06

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
889474AKLFActiveNLG24P1VFQFPN24CYesTubeCheck Availability
889474AKLFTActiveNLG24P1VFQFPN24CYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
889474 Final Data Sheet Datasheet PDF 205 KB Nov 11, 2015
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
show all (12)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 24, 2013
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016