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8L3010I - Block Diagram
8L3010I - Pinout


Crystal Or Differential to LVCMOS/LVTTL Clock Buffer

The 8L3010I is a low skew, 1-to-10 LVCMOS / LVTTL Fanout Buffer. The low impedance LVCMOS/LVTTL outputs are designed to drive 50? series or parallel terminated transmission lines. The 8L3010I is characterized at full 3.3V and 2.5V, mixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 2.5V/1.8V and 2.5V/1.5V output operating supply modes. The input clock is selected from two differential clock inputs or a crystal input. The differential input can be wired to accept a single-ended input. The internal oscillator circuit is automatically disabled if the crystal input is not selected.


  • Ten LVCMOS / LVTTL outputs up to 200MHz
  • Differential input pair can accept the following differential input levels: LVPECL, LVDSHCSL
  • Crystal Oscillator Interface
  • Crystal input frequency range: 10MHz to 40MHz
  • Output skew: 50ps (maximum) @ 3.3V/3.3V
  • Additive RMS phase jitter: 0.24ps (typical) @ 3.3V/3.3V
  • Synchronous output enable to avoid clock glitch
  • Power supply modes: Core / Output 3.3V / 3.3V 2.5V / 2.5V 3.3V / 2.5V 3.3V / 1.8V 3.3V / 1.5V 2.5V / 1.8V 2.5V / 1.5V
  • 5V input tolerance
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
10LVCMOS0.000000 - 200.0000000.000000 - 200.0000003HCSL, LVDS, LVPECL, Crystal12.5, 3.3500.24

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8L3010ANLGIActiveNLG32P3VFQFPN32IYesTrayCheck Availability
8L3010ANLGI8ActiveNLG32P3VFQFPN32IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
IDT8L3010I Final Datasheet Datasheet PDF 289 KB Feb 29, 2012
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
show all (12)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
PCN# : W1308-01 Change of Passivation Thickness Product Change Notice PDF 941 KB Sep 11, 2013
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016