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8S54011 - Block Diagram
8S54011 - Pin Assignment

8S54011

Low Skew,1-to-2,Differential-To-CML Fanout Buffer

The 8S54011I is a high speed 1-to-2 Differential-to-CML Fanout Buffer. The 8S54011I is optimized for high speed and very low output skew, making it suitable for use in demanding applications requiring only the highest performing devices. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVDS, LVPECL and CML to be easily interfaced to the input with minimal use of external components.

The 8S54011I is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications.

Features

  • Two differential CML output pairs
  • IN, nIN pair can accept the following differential input levels:
    LVPECL, LVDSCML
  • Maximum output frequency: 3.2GHz
  • Output skew: 5ps (typical)
  • Part-to-part skew: 100ps (maximum)
  • Additive phase jitter, RMS: 0.059ps (typical)
  • Propagation delay: 225ps (typical)
  • Operating supply modes:
    Core/Output
    2.5V/1.8V
    2.5V/1.2V
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Divider ValueOutput Skew (ps)Additive Phase Jitter Typ RMS (ps)
2CML0.000000 - 3200.0000000.000000 - 3200.0000001LVDS, LVPECL, CML12.51.2, 1.850.059

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8S54011ANLGIActiveNLG16VFQFPN16IYesTubeCheck Availability
8S54011ANLGI8ActiveNLG16VFQFPN16IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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8S54011I Data Sheet Datasheet PDF 457 KB Aug 27, 2012
Apps Notes & White Papers
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AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
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AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCNs & PDNs
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PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
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PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
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PCN# : A1309-01 Changed of Traceability Mark Format Product Change Notice PDF 439 KB Oct 11, 2013
Other
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IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
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IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 17, 2015
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High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 14, 2012