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8T39S04A Block Diagram
8T39S04A Pin Assignment

8T39S04A

Crystal or Differential to Differential Clock Fanout Buffer

The 8T39S04A is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by a single-ended clock.The selected signal is distributed to four differential outputs which can be configured as LVPECL, LVDS or HSCL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for a signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply.

Features

  • Two differential reference clock input pairs
  • Differential input pairs can accept the following input levels:
    LVPECL, LVDS, HCSL, HSTL and Single-ended
  • Crystal Oscillator Interface
  • Crystal input frequency range: 10MHz to 40MHz
  • Maximum Output Frequency
    LVPECL - 2GHz
    LVDS - 2GHz
    HCSL - 250MHz
    LVCMOS - 250MHz
  • Two banks, each has two differential output pairs that can be
    configured as LVPECL or LVDS or HCSL
  • One single-ended reference output with synchronous enable to
    avoid clock glitch
  • Output skew: 80ps (maximum), Bank A and Bank B at the same
    output level
  • Part-to-part skew: 200ps (typical), design target
  • Additive RMS phase jitter @ 156.25MHz, (12kHz - 20MHz):
    34.7fs (typical), 3.3V/ 3.3V
  • Supply voltage modes:
    VDD/VDDO
    3.3V/3.3V
    3.3V/2.5V
    2.5V/2.5V
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) packaging

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (fs)
4LVDS, LVPECL, HCSL0.000000 - 2000.0000000.000000 - 2000.0000003LVDS, HCSL, LVPECL, HSTL, LVCMOS, Crystal22.5, 3.33234.7

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8T39S04ANBGIActiveNBG32P1VFQFPN32IYesTrayCheck Availability
8T39S04ANBGI8ActiveNBG32P1VFQFPN32IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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8T39S04A Datasheet Datasheet PDF 801 KB May 27, 2016
Apps Notes & White Papers
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AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
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AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
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AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
show all (13)
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
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AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
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AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
Other
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IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016