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8T73S1802 - Block Diagram
8T73S1802 - Pin Assignment

8T73S1802

1:2 Clock Fanout Buffer and Frequency Divider

The 8T73S1802 is a fully integrated clock fanout buffer and frequency divider. The input signal is frequency-divided and then fanned out to one differential LVPECL and one LVCMOS output. Each of the outputs can select its individual divider value from the range of ÷1, ÷2, ÷4 and ÷8. Three control inputs EN, SEL0 and SEL1 (3-level logic) are available to select the frequency dividers and the output enable/disable state. The single-ended LVCMOS output is phase-delayed by 650ps to minimize coupling of LVCMOS switching into the differential output during its signal transition.

The 8T73S1802 is optimized to deliver very low phase noise clocks. The VBB output generates a common-mode voltage reference for the differential clock input so that connecting the VBB pin to an unused input (nCLK) enables to use of single-ended input signals. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. The 8T73S1802 can be used with a 3.3V or a 2.5V power supply. The device is a member of the high-performance clock family from IDT.

Features

  • High-performance fanout buffer clock and fanout buffer
  • Input clock signal is distributed to one LVPECL and one LVCMOS output
  • Configurable output dividers for both LVPECL and LVCMOS outputs
  • Supports clock frequencies up to 1000MHz (LVPECL) and up to 200MHz (LVCMOS)
  • Flexible differential input supports LVPECL, LVDS and CML
  • VBB generator output supports single-ended input signal applications
  • Optimized for low phase noise
  • 650ps delay between LVCMOS and LVPECL minimizes coupling between outputs
  • Supply voltage: 3.3V or 2.5V
  • -40°C to 85°C ambient operating temperature
  • 16 VFQFN package (3mm x 3mm)

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Divider ValueOutput Skew (ps)Additive Phase Jitter Typ RMS (ps)
2LVPECL, LVCMOS0.000000 - 1000.000000, 0.000000 - 200.0000000.000000 - 1000.0000001LVPECL, LVDS, CML22.5, 3.32.5, 3.31, 2, 4, 80.057

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8T73S1802NLGINot Recommended
NLG16VFQFPN16IYesTubeCheck Availability
8T73S1802NLGI/WActiveNLG16VFQFPN16IYesReelCheck Availability
8T73S1802NLGI8Not Recommended
NLG16VFQFPN16IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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8T73S1802 Data Sheet Datasheet PDF 657 KB Sep 1, 2015
Apps Notes & White Papers
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AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
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AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
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AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCNs & PDNs
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PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
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PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
Other
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IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016