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8T73S208i - Block Diagram
8T73S208i - Pin Assignment


2.5V/3.3V Differential LVPECL Clock Divider And Fanout Buffer

The 8T73S208 is a high-performance differential LVPECL clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks. The 8T73S208 is characterized to operate from a 2.5V and 3.3V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8T73S208 ideal for those clock distribution applications demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the reference source easy and reduce passive component count. Each output can be individually enabled or disabled in the high-impedance state controlled by a I2C register. On power-up, all outputs are enabled. 


  • One differential input reference clock
  • Differential pair can accept the following differential input levels: LVDS, LVPECLCML
  • Integrated input termination resistors
  • Eight LVPECL outputs
  • Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
  • Maximum input clock frequency: 1000MHz
  • LVCMOS interface levels for the control inputs
  • Individual output enable/disabled by I2C interface
  • Output skew: <60ps
  • Output rise/fall times: 350ps (maximum)
  • Low additive phase jitter, RMS: 0.182ps (typical)
  • Full 2.5V and 3.3V supply voltages
  • Available in Lead-free (RoHS 6) 32-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Divider ValueOutput Skew (ps)Additive Phase Jitter Typ RMS (ps)
8LVPECL0.000000 - 500.000000, 0.000000 - 250.000000, 0.000000 - 125.000000, 0.000000 - 1000.0000000.000000 - 1000.0000001LVDS, LVPECL, CML12.5, 3.32.5, 3.31, 2, 4, 8600.182

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8T73S208BNLGIActiveNLG32P3VFQFPN32IYesTrayCheck Availability
8T73S208BNLGI8ActiveNLG32P3VFQFPN32IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
Errata# : NEN-16-01 Datasheet Errata for 8T73S208BNLGI, 8T73S208BNLGI8 Datasheet PDF 64 KB Jun 26, 2016
8T73S208 Datasheet Datasheet PDF 526 KB Jun 15, 2016
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (11)
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
PCN# : A1403-03 Gold wire to Copper wire Product Change Notice PDF 42 KB Oct 15, 2014
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

Software & Tools

Title Type Format File Size Datesort icon
8T73S208I IBIS Model Model - IBIS ZIP 86 KB Nov 24, 2014