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8T79S838-08I

1-to-8 Differential to Universal Output Fanout Buffer

The IDT8T79S838-08I is a high performance, 1-to-8, differential input to universal output fanout buffer. The device is designed for signal fanout of high-frequency clock signals in applications requiring output frequencies generated simultaneously. The IDT8T79S838-08I is optimized for 3.3V and 2.5V supply voltages and a temperature range of -40°C to 85°C. The device is packaged in a space-saving 32 lead VFQFN package.

Features

  • Four banks of two output pairs
  • Individual output type control, LVDS or LVPECL, via serial interface
  • Individual outputs remain enabled while serial loading new device configurations
  • One differential PCLK, nPCLK input
  • PCLK, nPCLK input pair can accept the following differential input levels: LVPECL, LVDS levels
  • Maximum input frequency: 1.5GHz
  • LVCMOS control inputs
  • Individual output enable/disable control via serial interface
  • 2.375V to 3.465V supply voltage operation
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) packaging

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Output Skew (ps)
8LVDS, LVPECL0.000000 - 1500.0000000.000000 - 1500.0000001LVDS, LVPECL42.5, 3.32.5, 3.380

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8T79S838-08NLGIActiveNLG32P3VFQFPN32IYesTrayCheck Availability
8T79S838-08NLGI8ActiveNLG32P3VFQFPN32IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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IDT8T79S838-08I Datasheet Datasheet PDF 464 KB Jan 29, 2014
Apps Notes & White Papers
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AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
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AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
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AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCNs & PDNs
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PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
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PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
Other
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IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
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IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 17, 2015
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High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 14, 2012