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8V34S208I

1:8 LVDS Fanout Buffer with 2-Input Multiplexer for 1PPS Applications

The 8V34S208 is a differential 1:8 LVDS fanout buffer with a 2:1 input multiplexer. The device accepts DC to 250MHz clock and data signals and is designed for 1Hz clock /1PPS, 2kHz and 8kHz signal distribution. Controlled by the input mode selection pin, the differential input stages accept both rectangular or sinusoidal signals. The 8V34S208 also provides level translated LVCMOS/LVTTL outputs which are copies of the individual differential inputs CLKA and CLKB. The propagation delay of the device is very low, providing an ideal solution for clock distribution circuits with tight phase alignment requirements. The multiplexer select pin (SEL) allows to select one out of two input signals, which is copied to the four differential outputs.

 

Features

  • Designed for 1PPS, 2kHz, 8kHz and 10MHz GPS clock signal
    distribution
  • High speed 1:8 LVDS fanout buffer
  • Eight differential LVDS output pairs
  • 2:1 input multiplexer
  • Two selectable differential inputs accept LVDS and LVPECL
    signals
  • Accepts rectangular and sinusoidal input signals
  • Two input monitoring outputs (LVCMOS)
  • Max output frequency: 250 MHz
  • Additive RMS phase jitter:
    118fs (typical) at 100Mhz (12k-20Mhz)
  • Part-to-part skew: 250ps (maximum)
  • Propagation delay: 325ps (typical), LVDS output
  • Full 2.5V and 3.3V voltage supply
  • -40°C to 85°C ambient operating temperature
  • Lead-free 32-lead VFQFN (RoHS 6/6) packaging

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
10LVCMOS, LVDS0.000000 - 500.000000, 0.000000 - 250.000000, 0.000000 - 125.000000, 0.000000 - 1000.0000000.000000 - 1000.0000002LVPECL, SINUSOIDAL SIGNALS, LVDS12.5, 3.32.5, 3.3650.118

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8V34S208NLGIActiveNLG32P3VFQFPN32IYesTrayCheck Availability
8V34S208NLGI8ActiveNLG32P3VFQFPN32IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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8V34S208 Data Sheet Datasheet PDF 656 KB Nov 24, 2014
Apps Notes & White Papers
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AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (10)
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCNs & PDNs
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PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
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PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
Other
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IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016