Zero Delay Buffers (PLL)

IDT zero-delay buffers are PLL-based devices that regenerate the input clock signal with fanout to drive multiple loads. The delay through the device can be adjusted through an external feedback path. This allows precise control of the timing of the clock signals to the loads.

Zero-delay buffers provide a synchronous copy of the input clock at the outputs, usually without frequency translation. Simple frequency translation is possible when a simple divider is used for all outputs, including feedback output, to maintain clock synchronization.