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574 - Block Diagram
574 - Pinout


Zero Delay, Low Skew Buffer

The 574 is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs is connected directly to FBIN, the rising edge of each output is aligned with the rising edge of the input clock. External delay elements connected in the feedback loops will cause the outputs to occur before the inputs by the amount of propagation delay of the external element.


  • Packaged in 8 pin narrow SOIC, Pb (lead) free
  • Zero input-to-output delay
  • Four 1X outputs
  • Output to output skew is less than 150 ps
  • Output clocks up to 160 MHz at 3.3 V
  • External feedback path for output edge placement
  • Spread Smart™ technology works with spread spectrum clock generators
  • Full CMOS outputs with 18 mA output drive capability at TTL levels at 3.3 V
  • Advanced, low power, sub-micron CMOS process
  • Operating voltage from 3.0 to 5.5 V
  • Industrial temperature version available

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)
4LVCMOS20.000000 - 160.00000020.000000 - 160.0000001LVCMOS13.3, 53.3, 5

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
574MILFActiveDCG8SOIC8IYesTubeCheck Availability
574MILFTActiveDCG8SOIC8IYesReelCheck Availability
574MLFActiveDCG8SOIC8CYesTubeCheck Availability
574MLFTActiveDCG8SOIC8CYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
574 Datasheet Datasheet PDF 167 KB May 14, 2010
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
show all (10)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
System Applications and Design Guidelines with IDT’s Zero-Delay Buffers Application Note PDF 245 KB Sep 11, 2013
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Apr 14, 2016
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Feb 15, 2016
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB Oct 22, 2015
show all (7)
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB Jul 21, 2015
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 24, 2013
PCN# : A1208-01R1 Gold to Copper Wire Product Change Notice PDF 254 KB Dec 21, 2012
PCN# A-0607-06 MMT Thailand as Alternate Assembly Facility for PLCC, SOIC 150mil/300mil Product Change Notice PDF 223 KB Oct 6, 2006
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

Software & Tools

Title Type Format File Size Datesort icon
574 3.3V IBIS Model Model - IBIS ZIP 3 KB Mar 14, 2006