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872S480 - Block Diagram
872S480 - Pinout


Differential-to-HSTL Zero Delay Clock Generator

The 872S480 is a Zero Delay Clock Generator with hitless input clock switching capability. The 872S480 is ideal for use in redundant, fault tolerant clock trees where low jitter frequency synthesis are critical. The device receives two differential clock signals from which it generates two outputs with "zero" delay. The output and feedback dividers are configured to allow for a 1:1 frequency generation ratio. The 872S480 Dynamic Clock Switch (DCS) circuit continuously monitors both input clock signals. Upon detection of an invalid clock input (stuck LOW or HIGH for at least one complete clock period of the VCO feedback frequency), the loss of reference monitor will be set HIGH. If that clock is the primary clock, the DCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. Once the primary clock is restored to a good state, the DCS will automatically switch back to the primary clock input. The low jitter characteristics with input clock monitoring and DCS capability make the 872S480 an ideal choice for DDR3 applications requiring fault tolerant reference clocks.


  • Three differential HSTL output pairs
  • Selectable differential CLKx, nCLKx input pairs
  • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTLHCSL
  • Output frequency range: 350MHz to 950MHz
  • Input frequency range: 350MHz to 950MHz
  • VCO range: 970MHz to 2250MHz
  • External feedback for “zero delay” clock regeneration with configurable frequencies
  • Static phase offset: ±100ps (maximum)
  • Cycle-to-cycle jitter: 25ps (maximum)
  • Output skew: 20ps (maximum)
  • 3.3V operating voltage supply
  • Selectable DDR3 or DDR3 low voltage output
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)
2HSTL350.000000 - 950.000000350.000000 - 950.0000002HSTL, LVDS, LVPECL, HCSL13.33.3

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
872S480BKLFActiveNLG32P3VFQFPN32CYesTrayCheck Availability
872S480BKLFTActiveNLG32P3VFQFPN32CYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
ICS872S480 Datasheet Datasheet PDF 840 KB Apr 19, 2011
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (11)
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016