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MK2304-1 - Block Diagram


Zero Delay, Low Skew Buffer

The MK2304-1 is a low jitter, low skew, high performance Phase Lock Loop (PLL) based zero delay buffer for high speed applications. Based on IDT's proprietary low jitter PLL techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The MK2304-1 includes two banks of two outputs each 1X. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of all 4 outputs. Compared to competitive CMOS devices, the MK2304-1 has the lowest jitter. IDT manufactures the largest variety of clock generators and buffers and is the largest clock supplier in the world.


  • Packaged in 8-pin SOIC
  • Zero input-output delay
  • 2 banks of two 1X outputs
  • Output to output skew is less than 200 ps
  • Output clocks up to 133 MHz at 3.3 V
  • Full CMOS outputs with 8 mA output drive capability at TTL levels at 3.3 V
  • Spread SmartTM technology Works with Spread Spectrum clock generators
  • Advanced, low power, sub micron CMOS process
  • Operating voltage of 3.3 V
  • Available in industrial temperature range

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)
4LVCMOS10.000000 - 133.00000010.000000 - 133.0000001LVCMOS23.33.3

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
MK2304S-1ILFActiveDCG8SOIC8IYesTubeCheck Availability
MK2304S-1ILFTActiveDCG8SOIC8IYesReelCheck Availability
MK2304S-1LFActiveDCG8SOIC8CYesTubeCheck Availability
MK2304S-1LFTActiveDCG8SOIC8CYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
show all (9)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Apr 14, 2016
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Feb 15, 2016
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB Oct 22, 2015
show all (6)
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB Jul 21, 2015
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 24, 2013
PCN# : A1208-01R1 Gold to Copper Wire Product Change Notice PDF 254 KB Dec 21, 2012
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016