General Purpose Clock Generators, Synthesizers and Zero Delay Buffers
PLL Clock Generators
IDT clock generators are PLL-based products that generate different output frequencies from a common input frequency. Each peripheral in a system requires a different frequency to operate. IDT clock generators produce clock output frequencies within strict tolerances to the application they are sourcing. They use a simple, low cost, fundamental-mode quartz crystal or reference clock as the frequency reference, from which they generate low-jitter output clocks. Multiple copies of some frequencies may be provided to drive multiple loads. They also allow for frequency translation - either multiplication or division. IDT offers clock generators with both single ended and differential clock outputs. Some devices provide a programmable-skew feature allowing the user to adjust the timing of individual outputs. This provides flexibility for last minute clock skew management in the system. There are also devices available with an external feedback path, permitting precise control of clock signal timing to loads.
General Purpose Synthesizers
General purpose synthesizers are asynchronous clock sources with output frequencies readily selected with very high resolution (very small frequency steps). They use a simple, low-cost, fundamental-mode quartz crystal as the frequency reference, from which they synthesize low-jitter output clocks. Allowing on-the-fly configuration of the output frequency through either a parallel or serial interface, these flexible synthesizers support many wide frequency, low jitter clocking applications. IDT synthesizers use a PLL architecture that simultaneously provides low jitter performance with a wide frequency range. Using silicon device integration techniques, they offer more functionality than fixed frequency oscillators.
Zero Delay Buffers(ZDB)
Zero Delay Buffers are ideal for applications requiring synchronized clocking for FPGAs, CPUs, logic and synchronous memory. Zero-delay buffers are PLL-based devices that regenerate the input clock signal with fanout to drive multiple loads. Most devices allow the delay through the device to be adjusted through an external feedback path. This allows precise control of the timing of the clock signals to the loads. Zero-delay buffers provide a synchronous copy of the input clock at the outputs, usually without frequency translation. Simple frequency translation is possible when a single divider is used for all outputs, including feedback output, to maintain clock synchronization.
IDT’s Clock generators, synthesizers and zero delay families are available in a wide range of versions. Differential outputs such as LVPECL, LVDS, HCSL, CML, HSTL, as well as selectable outputs, are supported for output frequencies up to 3.2 GHz and single-ended LVCMOS outputs for frequencies up to 350 MHz. IDT’s PLL portfolio has devices supporting supply voltages from 1.2 V up to 3.3 V and that are available in the commercial and industrial temperature ranges.
Using an IDT PLL product has many benefits. Reducing the number of quartz crystals on a board improves reliability because crystals are highly susceptible to shock and vibration. Using a clock generator also reduces a customer’s board cost and space, Build of materials (BOM) and inventory levels by replacing multiple crystals and oscillators with one device. They are ideal for use in a large variety of systems, from personal computers to consumer electronics or industrial systems, as well as high-performance networking and communications systems.
|Part Number||Outputs (#)||Output Type||Output Freq Range (MHz)||Input Freq (MHz)||Inputs (#)||Input Signal||Output Banks (#)||Core Voltage (V)||Output Voltage (V)||Output Skew (ps)||Phase Noise Typ RMS (ps)||Phase Noise Max RMS (ps)||C-C Jitter Typ P-P (ps)||C-C Jitter Max P-P (ps)||Period Jitter Typ P-P (ps)||Period Jitter Max P-P (ps)||App Jitter Compliance||Prog. Clock||Prog. Interface||Reference Output||Spread Spectrum||Feedback Input|