Universal Frequency Translators (UFT™)
IDT FemtoClock® NG Universal Frequency Translators (UFT™) cover all your frequency synthesis and translation needs. Family members are available that support 1, 2, 3 or 4 PLL’s in a single package.
As a frequency synthesizer, a low-cost, readily-available fundamental mode crystal can be used to generate output frequencies that range from 1 MHz to 1.3 GHz. The internal architecture of the device allows any frequency of crystal from 16 MHz to 40 MHz to be used regardless of the frequency desired.
As a frequency translator, this family of devices accepts 1 or 2 input reference clocks per PLL from 8 kHz to 710 MHz, switching between them as necessary and generates any output frequency from 1 MHz to 1.3 GHz with no frequency translation error in most cases.
Family members support either one or two different pin-selectable configurations per PLL that may be pre-loaded into the internal One-Time Programmable (OTP) non-volatile memory for automatic operation directly from powerup, or an I2C serial interface can be used to set the desired configurations.
In addition to a crystal input, the UFT features two clock inputs per PLL and provides two outputs per PLL. Each output is individually programmable as LVPECL or LVDS. Versions of the UFT with single-ended outputs are also available. Selection between the two input references per PLL may be performed manually via either pin or register, or it may be performed automatically with revertive or non-revertive recovery.
Frequency Synthesizer Mode allows an arbitrary output frequency to be generated from a fundamental mode crystal input. The PLL feedback loop supports a fractional feedback divider. This allows the VCO operating frequency to be a non-integer multiple of the crystal frequency.
High-Bandwidth Frequency Translator Mode is used to translate one or two input clocks of the same nominal frequency into an unrelated output frequency, attenuating cycle-to-cycle jitter. Only the High-Bandwidth PLL loop is used. A pre-divider stage is available, enabling input frequencies up to 710 MHz.
Low-Bandwidth Frequency Translator Mode (Jitter Attenuator Mode) involves two PLL loops and is typically used to achieve precise output-to-input frequency translation ratios. The Low-Bandwidth PLL loop drives a digitally controlled crystal oscillator (DCXO) loop via an analog-to-digital converter. The phase detector is optimized to work with frequencies starting at 8 kHz. An external low-pass filter can be used.
|Part Number||Outputs (#)||Output Type||Output Freq Range (MHz)||Input Freq (MHz)||Inputs (#)||Input Signal||Output Banks (#)||Core Voltage (V)||Output Voltage (V)||Output Skew (ps)||Phase Noise Typ RMS (ps)||Phase Noise Max RMS (ps)||C-C Jitter Typ P-P (ps)||C-C Jitter Max P-P (ps)||Period Jitter Typ P-P (ps)||Period Jitter Max P-P (ps)||App Jitter Compliance||Prog. Clock||Prog. Interface||Reference Output||Abs. Pull Range Min. (± PPM)|