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843002I-41 - Block Diagram
843002I-41 - Pinout


700MHz,FemtoClock® VCXO Based SONET/SDH Jitter Attenuator

The 843002I-41 is a PLL based synchronous clock generator that is optimized for SONET/SDH line card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the 2nd PLL stage (typically 19.44MHz). The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock® VCO. PLL multiplication ratios are selected from internal lookup tables using device input selection pins. The device performance and the PLL multiplication ratios are optimized to support non-FEC (non-Forward Error Correction) SONET/SDH applications with rates up to OC-48 (SONET) or STM-16 (SDH). The VCXO requires the use of an external, inexpensive pullable crystal. VCXO PLL uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given line card application.

The 843002I-41 includes two clock input ports. Each one can accept either a single-ended or differential input. Each input port also includes an activity detector circuit, which reports input clock activity through the LOR0 and LOR1 logic output pins. The two input ports feed an input selection mux. "Hitless switching" is accomplished through proper filter tuning. Jitter transfer and wander characteristics are influenced by loop filter tuning, and phase transient performance is influenced by both loop filter tuning and alignment error between the two reference clocks.

Typical 843002I-41 configuration in SONET/SDH Systems:

  • VCXO 19.44MHz crystal
  • Input Reference clock frequency selections:
    19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz
  • Output clock frequency selections:
    19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz, Hi-Z


  • Two Differential LVPECL outputs
  • Selectable CLKx, nCLKx differential input pairs
  • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or single-ended LVCMOS or LVTTL levels
  • Maximum output frequency: 700MHz
  • FemtoClock VCO frequency range: 560MHz - 700MHz
  • RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz to 20MHz): 0.81ps (typical)
  • Full 3.3V or mixed 3.3V core/2.5V output operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Output Skew (ps)Phase Jitter Typ RMS (ps)Phase Jitter Max RMS (ps)
2LVPECL19.440000, 77.760000, 155.520000, 311.040000, 622.08000019.440000, 38.880000, 77.760000, 155.520000, 311.040000, 622.0800002HSTL, LVDS, SSTL, HCSL, LVCMOS, LVPECL23.32.5, 3.31500.810

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
843002AKI-41LFActiveNLG32P3VFQFPN32IYesTrayCheck Availability
843002AKI-41LFTActiveNLG32P3VFQFPN32IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
843002I-41 Datasheet Datasheet PDF 345 KB Sep 5, 2014
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-841 Pullable Crystal Selection and VCXO Tuning Application Note PDF 248 KB Sep 23, 2014
AN-831 The Crystal Load curve Application Note PDF 308 KB Sep 22, 2014
show all (19)
AN-849 Loop Filter Component Selection for VCXO Based PLLs Application Note PDF 132 KB May 14, 2014
AN-848 VCXO - Crystal Selection Application Note PDF 138 KB May 14, 2014
AN-847 VCXO - Absolute Pull Range Application Note PDF 70 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 7, 2014
AN-839 RMS Phase Jitter Application Note PDF 149 KB May 7, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-830 Quartz Crystal Drive Level Application Note PDF 59 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB Mar 12, 2014
AN-801 Crystal-High Drive Level Application Note PDF 109 KB Jan 15, 2014
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 15, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 24, 2013
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

Software & Tools

Title Type Format File Size Datesort icon
843002I-41 IBIS Model Model - IBIS ZIP 64 KB Feb 6, 2009