Synchronous Ethernet PLL
The 8V89307 is an integrated solution for the Synchronous Equipment Timing Source supporting EEC-Option1, EEC-Option2 clocks in Synchronous Ethernet equipment.
The device has a high quality DPLL to provide system clocks for node timing synchronization within a Synchronous Ethernet network. It also integrates an APLL for better jitter performance.
An input clock is automatically or manually selected. It supports three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations.
The device provides programmable DPLL bandwidths: 15 mHz to 560 Hz and damping factors: 1.2 to 20 in 5 steps. Different settings cover all clock synchronization requirements.
A stable oscillator is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm.
All the read/write registers are accessed through a microprocessor interface. The device supports Serial and I2C interfaces.
- Features 15 mHz to 560 Hz bandwidth
- Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet (SyncE)
- Supports GR-253-CORE (OC-192) and ITU-T G.813 (STM-64) jitter generation requirements
- Provides clocks for 1 Gigabit and 10 Gigabit Ethernet applications
- 3.3V supply voltage
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
|Outputs (#)||Output Type||Output Freq Range (MHz)||Input Freq (MHz)||Inputs (#)||Input Type||Output Banks (#)||Core Voltage (V)||Output Voltage (V)||Output Skew (ps)||Phase Jitter Typ RMS (ps)||Phase Jitter Max RMS (ps)|
|3||LVCMOS (1), LVPECL/LVDS (2)||1.000000 - 644.531250||1.000000 - 625.000000||3||LVCMOS (1), LVPECL/LVDS (2)||3||3.3||3.3||1.000|