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MK2049-45 - Block Diagram


3.3V Communications Clock PLL

The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication. Basic configuration is determined by a Mode/Frequency Selection Table. Loop bandwidth and damping factor are programmable via external loop filter component selection. Buffer Mode accepts a 10 to 50MHz input and will provide a jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x ICLK. In this mode the MK2049-45 is ideal for filtering jitter from high frequency clocks. In External Mode, ICLK accepts an 8 kHz clock and will produce output frequencies from a table of common communciations clock rates, CLK and CLK/2. This allows for the generation of clocks frequency-locked to an 8 kHz backplane clock, simplifying clock synchronization in communications systems. The MK2049-45 can be dynamically switched between T1, E1, T3, E3 outputs with the same 24.576 MHz crystal. ICS can customize these devices for many other different frequencies. Contact your ICS representative for more details.


  • Packaged in 20 pin SOIC
  • 3.3 V + 5% operation
  • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E
  • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz
  • Locks to 8 kHz + 100 ppm (External mode)
  • Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1 / x0.5 or x1 / x2 outputs
  • Exact internal ratios enable zero ppm error
  • Output rates include T1, E1, T3, E3, and OC3 submultiples
  • Available in Pb (lead) free package
  • See also the MK2049-34 and MK2049-36
  • Not recommended for new designs. Use the MK2049-45A.

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Output Skew (ps)Phase Jitter Typ RMS (ps)Phase Jitter Max RMS (ps)
3LVCMOS0.008000 - 51.84000010.000000 - 50.000000, 0.0080001LVCMOS33.33.3

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
MK2049-45SIObsoletePS20SOIC20INoTubeCheck Availability
MK2049-45SILFLast Time BuyPSG20SOIC20IYesTubeCheck Availability
MK2049-45SILFTRLast Time BuyPSG20SOIC20IYesReelCheck Availability
MK2049-45SITRObsoletePS20SOIC20INoReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
MK2049-45A Datasheet Datasheet PDF 235 KB May 17, 2010
MK2049-45 Datasheet Datasheet PDF 243 KB Jan 19, 2004
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-831 The Crystal Load curve Application Note PDF 308 KB Sep 22, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (14)
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-839 RMS Phase Jitter Application Note PDF 149 KB May 7, 2014
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 7, 2014
AN-830 Quartz Crystal Drive Level Application Note PDF 59 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB Mar 12, 2014
AN-800 Approved VCXO Crystals Application Note PDF 63 KB Jan 28, 2014
AN-801 Crystal-High Drive Level Application Note PDF 109 KB Jan 15, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 15, 2014
PDN# : CQ-15-05 Market Declined Quarterly PDN Product Discontinuation Notice PDF 623 KB Oct 29, 2015
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 24, 2013
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
External Loop Filters Solver Engineering ZIP 22 KB Jun 18, 2013
show all (4)
PLL External Loop Filter Calculator Engineering ZIP 19 KB Jun 18, 2013