The IDT 82V3391 is an integrated synchronous equipment timing source for Stratum 3, Stratum 4E, Stratum 4, SMC, EEC-Option 1 and EEC-Option 2 clocks in broadband wireline access, SONET, SDH, synchronous Ethernet, optical transport and wireless. A typical application receives as input multiple clock sources from synchronous Ethernet, optical TDM and PDH data interfaces, GPS timing sources and network time protocols such as IEEE 1588. IDT 82V3391 timing paths switches automatically or manually between free-run, locked and holdover mode. IDT 82V3391 can calibrate the ppm frequency of the master clock reference.

A standard microprocessor interface supports access to read and write registers through serial, parallel and stand-alone EPROM modes. Real time control of both digitally controlled oscillators allows direct-write frequency synthesis. The IDT 82V3391 Master/Slave operation allows two devices, working together, to provide the dual redundant system clock paths.